As High-Performance Computing (HPC) becomes increasingly prevalent and resource-intensive, there is a growing need for the development of more efficient job schedulers, which play a crucial role in the performance of HPC clusters. This dissertation manifests a comprehensive approach to this complex issue, contributing to three major components of the problem: (1) metrics of job packing efficiency and fairness, (2) advanced scheduling algorithms, and (3) job resource utilization prediction techniques. To ensure high relevance of the results, this study emphasizes scheduling objectives. Therefore, scheduling quality metrics are investigated first, yielding a set of metrics that allow comparing alternative schedules and evaluating scheduling goals trade-offs. The set of metrics enables the first comprehensive analysis of effects of different scheduling improvement approaches on several aspects of scheduling quality, covering a variety of list scheduling algorithms as well as constraint programming optimization schedulers. The contribution to the third research area covers techniques to measure and estimate resource usage data. It reports a first-of-a-kind evaluation of various job runtime prediction techniques in improving scheduling quality, demonstrates an approach capable of estimating job parameters beyond the runtime, and explores measuring resources consumed by a job in an HPC cluster. The dissertation concludes with a practical demonstration of these concepts through an I/O-aware scheduling prototype that measures real-time resource utilization, autonomously determines job resource requirements the scheduler needs, and implements full-featured multi-resource backfill scheduling that accounts for the specific properties of the parallel file system bandwidth resource. The study exhibits the advantages of further reducing I/O congestion—beyond the capability of generic I/O-aware scheduling—and presents the Workload-adaptive scheduling strategy that attains such improvement. This approach features a “two-group” approximation technique to maintain efficient performance regardless of zero-throughput job availability. An evaluation conducted on a real HPC cluster demonstrates the effectiveness of the novel strategy.

L'évolution de quelques paramètres structuraux (.suri.: - f o l i a i r e , volume de l'entre-noeud...) est décrite au cours de la croissance de onze espèces arborescentes ou buissonnantes. Ce t r a v a i l montre que la t r a n s i t i o n vers la sexualité est liée à une prédominance croissante de la surface assimilat r i c e par rapport à l'axe ("axes foliarisés"). Outre son intérêt d e s c r i p t i f , cette approche structurale permet donc de c i r c o n s c r i r e certaines conditions ontogéniques de la f l o r a i s o n .

L’évolution de la microélectronique suit plusieurs axes notamment la miniaturisation des éléments actifs (réduction de taille des transistors), et l’augmentation de la densité d’interconnexion qui se traduisent par la loi de Gordon Moore qui prédit que la densité d'intégration sur silicium doublerait tous les deux ans. Ces évolutions ont pour conséquence la réduction des prix et du poids des composants. L’hybridation ou flip chip est une technologie qui s’inscrit dans cette évolution, elle consiste en l’assemblage de matériaux hétérogènes. Dans cette étude il s‘agit d’un circuit de lecture Silicium et d’un circuit de détection InP ou GaAs assemblés par l’intermédiaire d’une matrice de billes d’indium. La connexion flip chip est basée sur l’utilisation d’une jonction par plots métalliques de faibles dimensions qui permet de diminuer les pertes électriques (faible inductance et faible bruit), une meilleure dissipation thermique, une bonne tenue mécanique. Enfin elle favorise la miniaturisation avec l’augmentation de la compacité et de la densité d’interconnexion.Les travaux de thèse se concentrent sur deux axes principaux. Le premier concerne l’hybridation par brasure avec la technologie des billes d’indium par refusion, et le second concerne l’hybridation par pression à température ambiante (nano-scratch) par l’intermédiaire des nanostructures (Nano-fils d’or, Nano-fils ZnO). Ces travaux ont permis la réalisation d’un détecteur InGaAs avec extension visible de format TV 640*512 pixels au pas de 15 µm. Ces travaux ont également permis la validation mécanique de l’assemblage d’un composant de format double TV 1280*1024 pixels au pas de 10 µm par cette même méthode de reflow. Pour l’axe hybridation à froid, nos travaux ont permis la validation d’une méthode de croissance de nano-fils ZnO par une voix hydrothermique à basse température (<90°C). / Evolution of microelectronics follows several major roads, in particular the size decrease of active elements (reduction of size of transistors), better electrical performances, high I/O density and smaller size. This revolution has been predicted by Gordon Moore who suggested that integrated circuits would double in complexity every 24 months. As a consequence, this evolution induces both the reduction of prices and the weight of components.The term flip chip describes the method of electrically connecting the die to the package substrate. Flip chip microelectronic assembly is the direct electrical connection of face-down (or flipped) integrated circuit (IC) chips onto substrates, circuit boards, or carriers, using conductive bumps on the chip bond pads. Flip chip offers the highest speed electrical performance, reduces the delaying inductance and capacitance of the connection, Smallest Size Greatest I/O Flexibility, Most Rugged, high I/O density and Lowest Cost.This thesis work study concentrates on two main directions. The first one concerns hybridization by means of the technology of Indium bumps associated to a reflow process and the second one is about pressure induced hybridization at low temperature using nanostructures (Nano-scratch). In this work, we have developed a complete process to assemble a focal plane array format of 640 x 512 pixels with a pitch of 15 µm. These studies also allowed the mechanical validation of hybridization of a focal plane arrays 1280*1024 pixels with a pitch of 10 µm. Concerning alternative technologies to flip chip reflow, we introduced and demonstrate the relevance of a method of growth of ZnO nanorods using low temperature wet chemical growth and further hybridization at ambient temperature.

Virtualization is one of the important enabling technologies for Cloud Computing which facilitates sharing of resources among the virtual machines. However, it incurs performance overheads due to contention of physical devices such as disk and network bandwidth. Various I/O applications having different latency requirements may be executing concurrently on different virtual machines provisioned on a single server in Cloud data-centers. It is pertinent that the performance SLAs of such applications are satisfied through intelligent scheduling and allocation of disk resources. The underlying disk scheduler at the server is unable to distinguish between the application requests being oblivious to the characteristics of these applications. Therefore, all the applica- tions are provided best effort services by default. This may lead to performance degradation for the latency sensitive applications. In this work, we propose a novel disk scheduling framework PriDyn (Dynamic Priority) which provides differentiated services to various I/O applications co-located on a single host based on their latency attributes and desired performance. The framework employs a scheduling algorithm which dynamically computes latency estimates for all concurrent I/O applications for a given system state. Based on these, an appropriate pri- ority assignment for the applications is determined which is taken into consideration by the underlying disk scheduler at the host while scheduling the I/O applications on the physical disk. The proposed scheduling framework is able to successfully satisfy QoS requirements for the concurrent I/O applications within system constraints. This has been verified through ex- tensive experimental analysis. In order to realize the benefits of differentiated services provided by the PriDyn scheduler, proper combination of I/O applications must be ensured for the servers through intelligent meta-scheduling techniques at the Cloud data-center level. For achieving this, in the second part of this work, we extended the PriDyn framework to design a proactive admission control and scheduling framework PCOS (P rescient C loud I/O S cheduler). It aims to maximize to Utilization of disk resources without adversely affecting the performance of the applications scheduled on the systems. By anticipating the performance of the systems running multiple I/O applications, PCOS prevents the scheduling of undesirable workloads on them in order to maintain the necessary balance between resource consolidation and application performance guarantees. The PCOS framework includes the PriDyn scheduler as an important component and utilizes the dynamic disk resource allocation capabilities of PriDyn for meeting its goals. Experimental validations performed on real world I/O traces demonstrate that the proposed framework achieves appreciable enhancements in I/O performance through selection of optimal I/O workload combinations, indicating that this approach is a promising step towards enabling QoS guarantees for Cloud data-centers.

The aim of this master’s thesis was to analyze the contemporary electronic throttles and the requirements imposed on them. Then to build the mathematical model, identify parameters of the given electronic throttle, proceed the verification and on its basis to build the simulation model. There were selected suitable control and high power components to control the electronic throttle. Due to the knowledge of these parameters the simulation model was extended. For this extended simulation model was designed the position cascade controller with speed and current control loop. Using the designed controller the implementation of the electronic throttle control and the available high power and control module was realized.

This diploma thesis is a part of HUMMER project. The project deals with three student’s development of two-wheeled unstable vehicle Segway type and its diminished laboratory model. This thesis deals with reviviscence of laboratory model, design of its control and realization of its actuating (a more detailed breakdown of tasks in the project is shown below). At the beginning of the work is presented reviewed study. The first part of study deals with similar models in the world, their construction and way of control. In the next part of reviewed study follows description of a real model and derivation of model basic equations, in the last part of search is given principle of operation of some used sensors. The next step was the selection and design of required electronics. In this capture are described all designed electronic modules and used sensors. There are also given parameters of used batteries and motors. The next task was the estimation of system parameters. The estimation was made by sections, in the capture is in detail described way of measuring data and structuring of estimation model. The penultimate step was design of PID and LQR controller using I/O card MF 624 and their comparing. Following thing was choice of better regulator and its implementation to the microprocessor. The last step was the realization of actuating driving of model by joystick and supreme PC.

Avläsning av tillståndet hos en mikrobrytare kräver att den ansluts till ett I/O hos exempelvis PLC, mikrokontroller eller annan lämplig utrustning. Forsmarks Kraft-grupp AB (FKA) och avdelningen för larm och telekommunikation (NEIT) ser ett behov av att på kärnkraftsanläggningen i Forsmark installera mikrobrytare på platser där det saknas anslutningsutrustning och förmedla dess tillstånd till ett övervakande system. I denna rapport presenteras ett förslag till teknisk lösning som uppfyller FKA:s behov genom att spegla ett I/O över TCP/IP-protokoll. Lösningen har tagits fram utifrån specifika önskemål från FKA. Funktionen ska bland annat övervaka två områden med mikrobrytare, larma för fel, ha egenövervakning, ta hänsyn till signalintegritet samt baseras på generell mikrokontrollutrustning. Vi-dare har en utvärdering av tillförlitligheten gjorts samt att funktionen har testats. Resultatet presenteras som en prototyputrustning där två mikrokontrollplattformar från Arduino har använts som bas och designen har skett utifrån ett feltolerant per-spektiv. Trippelmodulär redundans, watchdog-timer, dubbelbalanserad slinga och majoritetsvotering är några av de tekniker som tillämpats. Genom en kombination av programmering och föreslagna metoder har FKA:s önskemål uppnåtts. Tillförlitlighetsutvärderingarna visar att prototyputrustningen har en mean time between failure på ungefär 3,2 år samt att sannolikheten för felfri drift i 20,000 tim-mar är ungefär 50 %. Funktionstesterna visar på goda förutsättningar för långsiktig funktionalitet gällande I/O-spegling och larmhantering. Testerna avslöjar även före-komsten av falska larm vilket har föranlett förslag om debuggning av mjukvaran in-nan driftsättning. Rapporten avslutas med en diskussion kring de uppnådda resulta-ten samt föreslagna kompletteringar och utvecklingar av prototyputrustningen. / Reading the state of a microswitch requires it to be connected to an I/O of, for ex-ample, PLC, microcontroller, or other suitable equipment. Forsmarks Kraftgrupp AB (FKA) and the department of alarms and telecommunications (NEIT) have real-ized a need to install microswitches at Forsmarks nuclear power plant at places where there are no connection equipment and redistribute its state to a monitoring system. This report presents a proposal for a technical solution that meets FKA:s needs by mirroring an I/O over TCP/IP-protocol. The solution has been developed based on specific requirements from FKA. The function should, among other things, monitor two areas with microswitches, alarm for faults, have self-monitoring, consider signal integrity, and be based on general microcontroller equipment. Furthermore, an analysis of the reliability has been made and the function has been tested. The result is presented as a prototype equipment where two microcontroller plat-forms from Arduino have been used as a base and the design has been done from a fault tolerant perspective. Triple modular redundancy, watchdog timer, double-bal-anced loop and majority voting are some of the techniques used. Through a combi-nation of programming and proposed methods, FKA:s wishes have been achieved. The reliability assessments show that the prototype equipment has a mean time be-tween failure of about 3.2 years and that the probability of faultless operation for 20,000 hours is about 50 %. The function tests show good conditions for long-term functionality regarding I/O mirroring and alarm handling. The tests also reveal the presence of false alarms, which has prompted proposals for debugging the software before deployment. The report concludes with a discussion of the results achieved as well as proposed additions and developments of the prototype equipment.

The motivation for inception of this MSc. thesis which follows on from a term project of the same name was the transfer of the application for building private virtual OpenVPN networks from Windows XP operating system to Windows CE Embedded 6.0 platform. The project deals with virtual private networks in general and looks more closely at its implementation - OpenVPN. It also introduces the basic features of the Windows CE operating system. The project goes on to describe device drivers in NT-based Windows operating systems, the Windows Driver Model used, the NDIS network interface model and also the model of Windows CE drivers - the Stream Interface Model. The project continues with a~description of communication in OpenVPN application and primarily the role of TUN/TAP virtual network interfaces. This is followed by a proposal for transfer of TUN/TAP adapter drivers together with a description of limitations and necessary modifications between both platforms. As a result a TAP network device driver is implemented whose function is verified by test application that emulates the behaviour of a TUN adapter. The project concludes with an evaluation of the achieved results, the possibilities for further work on this theme and with the overall contribution of this project.

This work provides overview of creating of a simple driver for the BIOS flash memory by accessing the physical computer memory. Although, the BIOS is one of a system's core components, there is no standardized update mechanism approach. Purpose of thesis is to create module driver by taking advantage of existing interface subsystem MTD, to suggest and implement driver for one specific device to Linux kernel operating system. Also explains technique allowing write access to registers of the flash memory with utilization of configuration file.

<p>Agricultural vehicles use electronic control units (ECUs) as control system. HistoricallyECUs have only been equipped with a minimum of features. With therecent progress in electronics, which have made components faster, smaller andcheaper, the trend is now to integrate more advanced functionality into the ECUs.</p><p>Agricultural vehicles are present all over the world and they have to operateunder a wide variety of conditions. This put high requirements on the system andit is critical that a modern ECU can detect and locate errors. For an ECU to beable to operate on a world-wide market it is required to be flexible, expandableand robust. In addition to these requirements it is also wanted that an ECU havea long lifespan and a low cost.</p><p>In this thesis different problems that modern ECUs have to face are investigated.Suggestions of how to solve these problems are also presented. Thereare two focuses in the thesis, 1) how ECUs can acquire information from its inputs/outputs; and 2) the requirements of the ECU hardware.</p><p>This thesis does not aim to deliver a fully specified system description butrather to provide an overview of how an ECU can be designed and which problemsthat it has to face.</p><p>A selection of areas of ECU design which are investigated in this thesis are,1) typical inputs/outputs; 2) analog-to-digital converters and their application; 3)how multiplexers can be used; 4) requirements of general purpose inputs/outputs(GPIO); 5) monitoring of a controller area network (CAN); 6) power-supply requirementand monitoring; 7) monitoring of the vehicle’s battery; 8) memory; 9)requirement of the microcontroller (MCU);Agricultural vehicles use electronic control units (ECUs) as control system. HistoricallyECUs have only been equipped with a minimum of features. With therecent progress in electronics, which have made components faster, smaller andcheaper, the trend is now to integrate more advanced functionality into the ECUs.Agricultural vehicles are present all over the world and they have to operateunder a wide variety of conditions. This put high requirements on the system andit is critical that a modern ECU can detect and locate errors. For an ECU to beable to operate on a world-wide market it is required to be flexible, expandableand robust. In addition to these requirements it is also wanted that an ECU havea long lifespan and a low cost.In this thesis different problems that modern ECUs have to face are investigated.Suggestions of how to solve these problems are also presented. Thereare two focuses in the thesis, 1) how ECUs can acquire information from its inputs/outputs; and 2) the requirements of the ECU hardware.This thesis does not aim to deliver a fully specified system description butrather to provide an overview of how an ECU can be designed and which problemsthat it has to face.A selection of areas of ECU design which are investigated in this thesis are,1) typical inputs/outputs; 2) analog-to-digital converters and their application; 3)how multiplexers can be used; 4) requirements of general purpose inputs/outputs(GPIO); 5) monitoring of a controller area network (CAN); 6) power-supply requirementand monitoring; 7) monitoring of the vehicle’s battery; 8) memory; 9)requirement of the microcontroller (MCU);</p>