In this thesis, we proposed a simple yet novel multicast scheduling scheme for IEEE 802.16e wireless metropolitan area networks. Specifically, we want to solve the problem that how the base station schedules data messages in a multicast superframe such that mobile stations can receive their required multicast data and the total awake time of mobile stations is minimal. We first prove that this problem is NP-complete, and then propose a greedy k-approximation algorithm, named G-EEMS, whose running time is , where n is the total number of multicast data messages and k is the size of MBS (multicast and broadcast service) zone in a frame. Simulation results show that, in terms of energy throughput, G-EEMS significantly outperforms the existing scheme, called SMBC-D.

Doctor of Philosophy / Department of Electrical and Computer Engineering / Don M. Gruenbacher / Future technologies such as cognitive radio require flexible and reliable hardware architectures that can be easily configured and adapted to varying coding parameters. The objective of this work is to develop a flexible hardware encoder and decoder for low-density parity-check (LDPC) codes. The design methodologies used for the implementation of a LDPC encoder and decoder are flexible in terms of parity-check matrix, code rate and code length. All these designs are implemented on a programmable chip and tested. Encoder implementations of LDPC codes are optimized for area due to their high complexity. Such designs usually have relatively low data rate. Two new encoder designs are developed that achieve much higher data rates of up to 844 Mbps while requiring more area for implementation. Using structured LDPC codes decreases the encoding complexity and provides design flexibility. The architecture for an encoder is presented that adheres to the structured LDPC codes defined in the IEEE 802.16e standard. A single encoder design is also developed that accommodates different code lengths and code rates and does not require re-synthesis of the design in order to change the encoding parameters. The flexible encoder design for structured LDPC codes is also implemented on a custom chip. The maximum coded data rate of the structured encoder is up to 844 Mbps and for a given code rate its value is independent of the code length. An LDPC decoder is designed and its design methodology is generic. It is applicable to both structured and any randomly generated LDPC codes. The coded data rate of the decoder increases with the increase in the code length. The number of decoding iterations used for the decoding process plays an important role in determining the decoder performance and latency. This design validates the estimated codeword after every iteration and stops the decoding process when the correct codeword is estimated which saves power consumption. For a given parity-check matrix and signal-to-noise ratio, a procedure to find an optimum value of the maximum number of decoding iterations is presented that considers the affects of power, delay, and error performance.

This thesis presents a novel VLSI design of multi-code rate Low-Density Parity-Check code (LDPC) decoder for IEEE 802.16e standard. In order to support the different code rates adopted by the standard, this thesis proposes a programmable LDPC decoder architecture based on the edge-serial approach. This edge-serial architecture can perform the sequential check-node computation according to the internal sequence update commands. Any complex and irregular parity-check matrix can all be realized in the proposed architecture if the number of bit-nodes each check node connects does not exceed a certain bound. In addition to the high flexibility, this thesis also proposes several design optimization techniques suitable for the LDPC decoder. First, the designs of the LDPC decoders in the past all put more emphasis on the realization of check node function. This thesis instead applies a novel bit-node major approach which can lead to more compact design. Secondly, a fine-grain message update method is used which allows more rapid message passing such that the decoder can converge in less cycles. In addition, almost half of the message memory can be reduced. Furthermore, based on the bit-node major decoder design, the early termination scheme can be utilized to partially terminate the function of some bit nodes to reduce the decoding cycles. The other salient features also include the rescheduling of the message update order to allow the overlap of different decoding iterations in order to reduce effect of the possible message update hazard due to the long internal pipeline latency. Based on the proposed optimization methods, our experimental results show that the hardware cost can be reduced by 23.1% while the decoding cycles can be reduced by 27.4%. The proposed LDPC decoder architecture has been realized by using 0.18 µm technology with the total gate count of 316k. Our experimental shows that the proposed LDPC decoder can run up to 235 MHz and deliver the average of 116 Mbps throughput.

A circuit design of Low Density Parity Check (LDPC) decoder for IEEE 802.16e systems is with new overlapped method is proposed in this thesis. This circuit can be operated with 19 modes which are corresponding to block sizes of 576, ¡K, 2304. LDPC decoders can be implemented by using iterations with Variable Node and Check Node Processes. The hardware utilization ratio, which can be enhanced from 50% to 100% by using our proposed overlapped method, is better than traditional overlapped method. In [2], the traditional overlapped method utilization ratio just can be enhanced from 50% to 75% for IEEE 802.16e LDPC decoder with code rate 1/2. Under the same operating frequency, our proposed method can further increase 25% when compared with traditional overlapped method [2]. In this thesis, we also propose two circuit architectures to increase the operating frequency. First, we use a faster comparison circuit in our comparison unit [1]. Second, we use Carry Save Adder¡]CSA¡^method [8] to replace the common adder unit. The circuit is carried out by TSMC CMOS 0.18£gm 1P6M process with chip area 3.11 x 3.08 mm2. In the gate level simulation, the output data rate of this circuit is above 78.4MHz, so the circuit can meet the requirement of IEEE 802.16e system.

One of the major applications driving wireless network services is video streaming, which is based on the ability to simultaneously multicast the same video contents to a group of users, thus reducing the bandwidth consumption. On the other hand, due to slow progress in battery technology, the investigation of power saving technologies becomes important. IEEE 802.16e (also known as Mobile WiMAX) is currently the international MAC (medium access control) standard for wireless metropolitan area networks. However, in 802.16e, the power saving class for multicast traffic is designed only for best-effort-based management operations. On the other hand, SMBC-AMC adopts the concepts of ¡§multicast superframe¡¨ and ¡§logical broadcast channel¡¨ to support push-based multicast applications. However, SMBC-AMC requires that (1) the number of frames in each logical broadcast channel must be equal, (2) all mobile stations must have the same duty cycle, and (3) the base station must use the same modulation to send data in a frame. These imply that SMBC-AMC is too inflexible to reach high multicast energy throughput. In this thesis, we propose cross-layer energy efficient multicast scheduling algorithms, called EEMS-AMC, for scalable video streaming. The goal of EEMS-AMC is to find a multicast data scheduling such that the multicast energy throughput of a WiMAX network is maximum. Specifically, EEMS-AMC has the following attractive features: (1) By means of admission control and the restriction of the multicast superframe length, EEMS-AMC ensures that the base layer data of all admitted video streams can be delivered to mobile stations in timeliness requirements. (2) EEMS-AMC adopts the greedy approach to schedule the base layer data such that the average duty cycle of all admitted stations can approach to the theoretical minimum. (3) EEMS-AMC uses the metric ¡§potential multicast throughput¡¨ to find the proper modulation for each enhancement layer data and uses the metric ¡§multicast energy throughput gain¡¨ to find the near-optimal enhancement layer data scheduling. Simulation results show that EEMS-AMC significantly outperforms SMBC-AMC in terms of average duty cycle, multicast energy throughput, multicast packet loss rate, and normalized total utility.

With the advent of new multimedia applications the demand for in time delivery of data is increased as compared to the reliability. Usually the Transport Layer Protocols, User Datagram Protocol (UDP) and Transmission Control Protocol (TCP) are used to transfer the data over the IP based network like Internet. TCP provides a reliable mechanism to transfer the data but its reliable mechanism results in increase in delay. UDP lacks in providing any acknowledgment mechanism and it does not provide any congestion control mechanism also. However the unreliable behavior of UDP results in less delay in data transfer. Now a days one of the important issues is the Quality of Service (QoS) assurance as the behavior of transport layer protocols can affect the QoS. So in order to avoid these issues some new transport layer protocols have been developed by Internet Engineering Task Force (IETF). Two important transport layer protocols, Datagram Congestion Control Protocol (DCCP) and Stream Control Transmission Protocol (SCTP) are used in this study. DCCP is specially designed to avoid congestion in the network. DCCP is suitable for in time delivery of data and also for its congestion control mechanism. DCCP is an unreliable transport layer protocol, as the real time applications demands for in time delivery rather than reliability. SCTP is another transport layer protocol that provides reliable data transfer. In this research work performance of SCTP, DCCP and UDP has been evaluated using MPEG-4 video over Mobile WiMAX/IEEE 802.16e. The performance of these three transport layer protocols is analyzed in terms of performance metrics like packet loss, jitter, delay and throughput. By analyzing these performance measures it is found that the performance of DCCP and SCTP is much better as compared to UDP but DCCP gives much better performance then SCTP when compared in terms of throughput and packet loss. Comparing SCTP and DCCP with UDP in terms of delay and jitter shows that UDP has less delay and jitter as compared to SCTP and DCCP, but because of less throughput and large number of packet loss, UDP can badly degrade the video quality. So, it is found that the DCCP is the most suitable transport layer protocol for transportation of MPEG-4 traffic over Mobile WiMAX/IEEE 802.16e.

With the rapid migration of physical layer design of radio towards software, it becomes necessary to select or develop the platform and tools that help in achieving rapid design and development along with flexibility and reconfigurability. The availability of field programmable gate arrays (FPGAs) has promoted the concept of reconfigurable hardware for software defined radio (SDR). It enables the designer to create high speed radios with flexibility, low latency and high throughput. Generally, the traditional method of designing FPGA based radios limits productivity. Productivity can be improved using Model based design (MBD) tools. These tools encourage a modular way of developing waveforms for radios. The tools based on MBD have been the focus of recent research exploring the concept of the platform independent model (PIM) and portability across platforms by the platform specific model (PSM). The thesis presented here explores the tools based on MBD to achieve prototyping for wireless standards like IEEE 802.11a and IEEE 802.16e on reconfigurable hardware. It also describes the interfacing of the universal software radio peripheral (USRP2), acting as a radio frequency (RF) front end, with an additional FPGA board for baseband processing. / Master of Science