Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and linearizer design techniques. Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel. A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives. Tunable matching networks are implemented utilizing varactor stacks in a &Pi / con

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power ampli

L’objectif de ce travail est d’aborder la conception de réseaux d’adaptation d’impédance accordable (RAA) dans deux contextes bien distincts en radiofréquences : le RAA en faible signal et le RAA en fort signal.Concernant les aspects faible signal, des critères de performance de RAA ont été établis et étudiés. Une nouvelle expression générale de l’efficacité d’un RAA a été développée. Elle permet de prédire le rendement d’un RAA à partir des facteurs de qualité des composants dont on dispose dans une technologie donnée et du rapport de transformation à réaliser. Des abaques de couverture d’impédances en fonction des pertes d’insertion ont été calculés. Ils mettent en évidence les régions de couverture où le RAA apporte une amélioration à la performance du système, pour diverses topologies de RAA.Un démonstrateur sur PCB a été réalisé. Il est constitué de deux RAA, qui assurent l’adaptation simultanée d’un amplificateur de puissance sur une large plage d’impédances, comprises dans un cercle de l’abaque de Smith d’équation VSWR < 5 :1. La zone de couverture a été mesurée et présentée en fonction des pertes d’insertion, qui mettent en évidence les régions où les RAA contribuent à l’amélioration de la performance de l’amplificateur et celles où les pertes d’insertion du RAA n’arrivent pas à compenser le gain du à la réduction des coefficients de réflexion.Dans une seconde partie, la conception de RAA en fort signal a été traitée. L’objectif a été de présenter à la sortie d’un amplificateur de puissance les impédances qui optimisent son efficacité pour chaque puissance de travail. Un démonstrateur en technologie CMOS SOI 130 nm a été conçu et simulé. Il consiste en un amplificateur de puissance pour le standard WCDMA, fonctionnant à 900 MHz, et un RA accordable par des varactors MOS, capable de générer les impédances optimales correspondant à des puissances de sortie comprises entre 20 et 30 dBm. Les résultats ont mis en évidence le bénéfice apporté par l’insertion d’un RA accordable par rapport à un RA fixe. / The aim of this research was the design of tunable matching networks, in two different contexts: the TMN at low and high signals.Performance criteria of TMN were studied. A general expression has been developed that estimates the TMN efficiency in function of the quality factor of the components used. The impedance coverage of different RAA topologies was plotted in function of the insertion losses.For the small signal, we designed a prototype in PCB, composed by two TMN, which ensure the simultaneous matching of a power amplifier in a wide range of impedances, included in a circle of the Smith chart VSWR < 5: 1. The coverage area was measured and presented in function of the insertion losses, emphasizing the areas where the TMN contribute to improve the amplifier performance and those where insertion losses of the TMN are not able to compensate gain with the reduction of the reflection coefficients.Subsequently, we discussed the design of TMN for the large signal. The objective is to present at the output of a power amplifier, the impedances that optimize efficiency for each power of operation. A 130 nm SOI prototype was designed and simulated, consisting of a power amplifier for WCDMA standard, 900 MHz, and a MN tunable by MOS varactors able to produce the optimal impedances corresponding to an output power between 20 and 30 dBm. The results showed the benefit provided by inserting a tunable MN compared to a fixed one.

L'impédance d'entrée d'une antenne miniature est fortement affectée par des facteurs environnementaux à l'origine de pertes de puissance réduisant l'efficacité énergétique des têtes radiofréquences dans les applications RF, en particulier dans la télémétrie des implants cardiaques. Le but de mes études est de développer une unité de calibration d'impédance d'antenne très faible consommation capable d'adapter toute variation de l'impédance d'entrée de l'antenne à l'impédance de la source radiofréquence. La première partie de mon étude est axée sur la conception au niveau système d'une approche nouvelle de calibration automatique du système. Un réseau d'adaptation automatique d'impédance sans coupleur et fonctionnant de façon directe est étudié et permet d'optimiser la taille du dispositif, la vitesse de l'adaptation, la consommation d'énergie et les performances globales. Deuxièmement, une nouvelle méthode de synthèse du réseau d'adaptation variable est proposée pour réduire fortement la complexité globale de l'algorithme d'adaptation. La troisième partie de mon étude est axée sur la fabrication d'un démonstrateur hybride fonctionnant dans la bande médicale MICS afin de valider le concept auto adaptatif d'impédance. Un banc expérimental qui comprend une antenne immergée dans son milieu connectée au démonstrateur piloté par un microcontrôleur a été mis en place et a permis d'atteindre un coefficient de réflexion jusqu'à -30dB avec un temps de calibration inférieur à 1ms. La dernière partie de mon travail consiste à concevoir le circuit d'adaptation automatique d'impédance d'antenne très faible consommation fonctionnant dans la bande ISM 2.4GHz en utilisant la technologie CMOS 0.13um. Antenna input impedance is highly affected by environmental factors increasing the losses or reducing the power efficiency of the radiofrequency transceiver in many RF applications such as in implantable pacemaker device telemetry. The purpose of my study is to develop a low power fully integrated antenna-impedance tuning unit to match any variation of the antenna impedance to the source. The first part of my study is focused on the system-level design of a new approach to automatically match the system. A couplerless single step automatic matching network is investigated to optimize the die size, the speed, the power consumption and the overall performance. Second, a new method for synthesizing an automatic matching network is developed reducing strongly the overall complexity of the matching algorithm. The third part of my study is focused on the fabrication of a hybrid demonstrator operating at the Medical Implantable Communication Service (MICS) frequency band to validate the concept. An experimental set-up including the antenna tuning unit, a microcontroller and a pacemaker antenna connected to the demonstrator was done achieving a reflection coefficient up to -30dB, an overall tuning time less than 1ms. The last part of my work is to design the entire automatic matching network circuit in 0.13um CMOS technology including a front-end transceiver designed under ultra low power constraints and operating at 2.4GHz ISM frequency band. The additional items overall power consumption is less than 1.5mW under 1.2V supply voltage.

L'impédance d'entrée d'une antenne miniature est fortement affectée par des facteurs environnementaux à l'origine de pertes de puissance réduisant l'efficacité énergétique des têtes radiofréquences dans les applications RF, en particulier dans la télémétrie des implants cardiaques. Le but de mes études est de développer une unité de calibration d'impédance d'antenne très faible consommation capable d'adapter toute variation de l'impédance d'entrée de l'antenne à l'impédance de la source radiofréquence. La première partie de mon étude est axée sur la conception au niveau système d'une approche nouvelle de calibration automatique du système. Un réseau d'adaptation automatique d'impédance sans coupleur et fonctionnant de façon directe est étudié et permet d'optimiser la taille du dispositif, la vitesse de l'adaptation, la consommation d'énergie et les performances globales. Deuxièmement, une nouvelle méthode de synthèse du réseau d'adaptation variable est proposée pour réduire fortement la complexité globale de l'algorithme d'adaptation. La troisième partie de mon étude est axée sur la fabrication d'un démonstrateur hybride fonctionnant dans la bande médicale MICS afin de valider le concept auto adaptatif d'impédance. Un banc expérimental qui comprend une antenne immergée dans son milieu connectée au démonstrateur piloté par un microcontrôleur a été mis en place et a permis d'atteindre un coefficient de réflexion jusqu'à -30dB avec un temps de calibration inférieur à 1ms. La dernière partie de mon travail consiste à concevoir le circuit d'adaptation automatique d'impédance d'antenne très faible consommation fonctionnant dans la bande ISM 2.4GHz en utilisant la technologie CMOS 0.13um. / Antenna input impedance is highly affected by environmental factors increasing the losses or reducing the power efficiency of the radiofrequency transceiver in many RF applications such as in implantable pacemaker device telemetry. The purpose of my study is to develop a low power fully integrated antenna-impedance tuning unit to match any variation of the antenna impedance to the source. The first part of my study is focused on the system-level design of a new approach to automatically match the system. A couplerless single step automatic matching network is investigated to optimize the die size, the speed, the power consumption and the overall performance. Second, a new method for synthesizing an automatic matching network is developed reducing strongly the overall complexity of the matching algorithm. The third part of my study is focused on the fabrication of a hybrid demonstrator operating at the Medical Implantable Communication Service (MICS) frequency band to validate the concept. An experimental set-up including the antenna tuning unit, a microcontroller and a pacemaker antenna connected to the demonstrator was done achieving a reflection coefficient up to -30dB, an overall tuning time less than 1ms. The last part of my work is to design the entire automatic matching network circuit in 0.13um CMOS technology including a front-end transceiver designed under ultra low power constraints and operating at 2.4GHz ISM frequency band. The additional items overall power consumption is less than 1.5mW under 1.2V supply voltage.

A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures. / Dissertation (MEng)--University of Pretoria, 2012. / Electrical, Electronic and Computer Engineering / unrestricted