Το αντικείμενο της παρούσας διπλωματικής εργασίας είναι ο σχεδιασμός και η υλοποίηση ενός ταλαντωτή εμβολής, ο οποίος θα μπορεί να χρησιμοποιηθεί και ως διαιρέτης συχνοτήτων. Ο ταλαντωτής και ο διαιρέτης συχνοτήτων, αποτελούν εξέχουσας σημασίας δομικά στοιχεία των RF πομποδεκτών και τοποθετούνται κατά κύριο λόγο μέσα στο βρόχο κλειδώματος φάσης-PLL, ο οποίος επιλέγεται ως συνθέτης συχνοτήτων στα περισσότερα ασύρματα τηλεπικοινωνιακά συστήματα. Αφού μελετήσαμε τη δομή και τις κυριότερες τοπολογίες που χρησιμοποιούνται στη σχεδίαση των ταλαντωτών, προχωρήσαμε στην ανάλυση της εφαρμογή της μεθόδου της εμβολής (injection locking), με σκοπό τη βελτίωση των χαρακτηριστικών της εξόδου τους και ιδιαίτερα τη μείωση του θορύβου φάσης. Επίσης, περιγράφονται τα βασικά χαρακτηριστικά των αναλογικών και των ψηφιακών διαιρετών, ενώ δίνεται ιδιαίτερη έμφαση στην ανάλυση της λειτουργίας των αναλογικών διαιρετών συχνότητας που βασίζονται σε ταλαντωτές εμβολής και είναι ευρύτερα γνωστοί ως injection-locked διαιρέτες συχνότητας (ILFDs). Η επιλογή για περαιτέρω μελέτη και υλοποίηση ενός Colpitts και ενός διαφορικού ταλαντωτή, βασίστηκε στα πλεονεκτήματα που παρουσιάζουν οι συγκεκριμένες τοπολογίες, με αποτέλεσμα την ευρεία χρήση τους σε RF εφαρμογές υψηλών συχνοτήτων. Επίσης οι ταλαντωτές εμβολής που προκύπτουν από τους ταλαντωτές αυτούς, επιδεικνύουν χαμηλή κατανάλωση ισχύος και πολύ καλή συμπεριφοράς ως προς τον θόρυβο φάσης. Ως συχνότητα λειτουργίας των προτεινόμενων κυκλωμάτων, επιλέχθηκε η πολύ σημαντική για τα ασύρματα συστήματα τηλεπικοινωνιών, συχνότητα των 5GHz. Προτείνεται και υλοποιείται λοιπόν ένας Colpitts ταλαντωτής και ο αντίστοιχος ταλαντωτής εμβολής, όπου όπως αποδεικνύεται τόσο από τις εξομοιώσεις όσο και από τα πειραματικά αποτελέσματα, μπορεί να λειτουργεί ως διαιρέτης συχνότητας δια-2 (Divide-by-2 ILFD). Από τα αποτελέσματα που προέκυψαν από τη μέτρηση του υλοποιημένου ταλαντωτή εμβολής, γίνεται ακόμη αντιληπτό ότι ο θόρυβος φάσης είναι εμφανώς βελτιωμένος, όπως αναμενόταν λόγω της εφαρμογής του σήματος εμβολής. Τέλος, σχεδιάστηκε και εξομοιώθηκε ένας διαφορικός ταλαντωτής (differential oscillator), από τον οποίο με κατάλληλη τροποποίηση της τοπολογίας του, προέκυψε ένας injection-locked divide-by-2 διαιρέτης συχνότητας. Το συγκεκριμένο κύκλωμα χρησιμοποιείται ευρέως για τη λειτουργία της διαίρεσης δια-2, εξαιτίας του ότι η τοπολογία του παρέχει ένα φυσικό divide-by-2 injection σημείο. / The subject of the present diplomatic project is the design and implementation of an injection locked oscillator, which might also be used as a frequency divider. The oscillator and the frequency divider, constitute distinguished important structural elements of RF transceivers and are mostly placed into the phase-locked-loop (PLL), which is selected as frequency synthesizer in most wireless telecommunications systems. After we studied the structure and the main topologies used in the design of oscillators, we advanced in the analysis and the application of injection locking method, aiming at the improvement of characteristics of their output and particularly the reduction of phase noise. Also, the basic characteristics of analog and digital dividers are described, while particular emphasis is given in the analysis of operation of analog frequency dividers that is based on injection-locked oscillators, more widely known as injection-locked frequency dividers (ILFDs). The choice for further study and implementation of a Colpitts and differential oscillator, was based on the advantages of the particular topologies, which result in their wide use in high-frequencies RF applications. Also the injection-locked oscillators that result from these oscillators, demonstrate low power consumption and very good behavior as far the phase noise. As operation frequency for the proposed circuits, was selected the very important for the wireless telecommunications systems, frequency of 5GHz. Therefore, it is proposed and implemented a Colpitts oscillator and the corresponding injection-locked oscillator, where as it is proved by the simulations as much as by the experimental results, can function as a divide-by-2 injection-locked frequency divider. From the results that resulted from the measurement of implemented injection-locked oscillator, it becomes clear that the phase noise is obviously improved, as it was expected due to the application of the injection signal. Finally, a differential oscillator was designed and simulated, from which with suitable modification of its topology, resulted a divide-by-2 injection-locked frequency divider. This particular circuit is used widely for the operation of division by-2, because its topology provides a natural divide-by-2 injection point.

This thesis uses injection-locked oscillators to realize spectrum and vital sign sensor. At first, the thesis discusses the factors to affect the locking range based on Adler¡¦s equation, and adopts an increase of injection power to enlarge the locking range. Then, the circuit simulation using ADS is carried out to predict the output response of an injection-locked oscillator. As an implementation result, a CMOS chip of an injection-locked oscillator achieves 70 MHz locking range at -17.5 dBm injection power. In addition, a CMOS FM demodulator is realized with the injection-locked oscillator, showing that the chip can demodulate the FSK signal with a minimum frequency deviation of 350 KHz, a minimum input power of -39.5 dBm, and a maximum data rate of 40 Mbps. With the help of the above CMOS chips, a spectrum sensor and a vital sign sensor are realized. In the test, the spectrum sensor can measure a minimum signal power of -100 dBm at a scan speed of 100 MHz/0.5 ms, while the vital sign sensor can detect the breathing and heartbeat rate at a sensing distance of 80 cm.

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012

The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Oct. 1, 2012 - Oct. 1, 2014

The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

High-power, single-frequency, narrow-linewidth lasers emitting at tailored wavelength are desired for many applications, especially for precision spectroscopy. By way of a free-space resonator, optically pumped semiconductor lasers (OPSLs), a.k.a. vertical external-cavity surface-emitting lasers (VECSELs), can provide near diffraction-limited, high-quality Gaussian beams and are scalable in output power. Free space resonators also allow the insertion of the birefringent filter and the etalon to enforce single-frequency operation. In addition, the emission wavelengths of OPSLs are tailorable through bandgap engineering. These advantages above make OPSL a strong candidate of laser sources for spectroscopic applications including atomic spectroscopy as well as optical lattice clocks. In this research, a single-frequency laser source with high power is demonstrated by applying the injection-locking technique on OPSLs for the first time. The behaviors of the injection-locked OPSL are studied by varying parameters such as output coupling, injection wavelengths and injection power. It was found that the best injection wavelength is by approximately 2 nm shorter than the free-running slave laser at any given pump power. Below the lasing threshold for free-running operation, the laser starts the stimulated emission process as soon as it is pumped, working as a resonant amplifier. With proper parameters, the output power of the injection-locked laser exceeds the output power of its free-running condition. Over 9 W of single-frequency output power at 1015 nm is achieved. The output beam is near-diffraction-limited with Mₓ² = 1.04 and My² = 1.02. By analyzing the surface photoluminescence (PL) and the output performance of the laser, the saturation intensity of OPSLs is estimated to be 100 kW/cm² when the passive loss of 1.4% is assumed. The injection-locked system adds fairly low phase noise to that of the master laser. By measuring the beat note between the master laser and the injection-locked laser, the RMS values of the phase noise are 0.112 rad and 0.081 rad when using the T = 3% and T = 4% output couplers respectively.

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye. In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye. In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.

This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with self-injection using 0.18-micrometer CMOS technology. The synthesizer is used for a multi-band multi-polarization radar system operating in the K- and Ka-band. The synthesizer is a fully integrated concurrent tri-band, tri-output phase-locked loop (PLL) with divide-by-3 injection locked frequency divider (ILFD). A new locking mechanism for the ILFD based on the gain control of the feedback amplifier is utilized to enable tunable and enhanced locking range which facilitates the attainment of stable locking states. The PLL has three concurrent multiband outputs: 3.47-4.313 GHz, 6.94-8.626 GHz and 19.44-21.42-GHz. High second-order harmonic suppression of 62.2 dBc is achieved without using a filter through optimization of the balance between the differential outputs. The proposed technique enables the use of an integer-N architecture for multi-band and microwave systems, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption. The 1/2 dual-ILFD with wide locking range and low-power consumption is analyzed and designed together with a divide-by-2 current mode logic (CML) divider. The 1/2 dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (QL) and output current amplitude (iOSC) simultaneously. The 1/2 dual-ILFD achieves a locking range of 692 MHz between 7.512 and 8.204 GHz. The new 1/2 dual-ILFD is especially attractive for microwave phase-locked loops and frequency synthesizers requiring low power and wide locking range. The 3.5-GHz divide-by-3 (1/3) ILFD consists of an internal 10.5-GHz Voltage Controlled Oscillator (VCO) functioning as an injection source, 1/3 ILFD core, and output inverter buffer. A phase tuner implemented on an asymmetric inductor is proposed to increase the locking range. The other divide-by-3 ILFD utilizes self-injection technique. The self-injection technique substantially enhances the locking range and phase noise, and reduces the minimum power of the injection signal needed for the 1/3 ILFD. The locking range is increased by 47.8 % and the phase noise is reduced by 14.77 dBc/Hz at 1-MHz offset.

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics. / The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.