Electrical signals produced in the human body can be used for medical diagnosis and research, treatment of diseases, pilot safety etc. These signals are extracted using an electrode (or transducer) to convert the ion current in the body to electron current. After the electrode, the very low amplitude extracted signal is amplified by an analog frontend that typically consists of an instrumentation amplifier (IA), a programmable gain amplifier (PGA), and a low pass filter (LPF). The output of the analog frontend is converted to digital signal by an analog to digital converter (ADC) for subsequent processing in the digital domain. This thesis discusses the circuit design challenges of the analog frontend instrumentation amplifier, compares existing circuit topologies used to implement the IA and proposes a new frontend IA. The proposed circuit uses the Current Balancing Instrumentation Amplifier (CBIA) topology to achieve high gain accuracy over a wide range of the output impedance. In addition it uses common circuit design techniques such as chopper modulation to achieve low flicker noise corner frequency, high common mode rejection (CMRR) and low noise efficiency factor (NEF). The proposed circuit has been implemented in the 0.5um CMOS ON-semiconductor process and consumes 16uW of power. The post-layout simulated gain accuracy is better than 94% for gain values from 20dB to 60dB, measured NEF is 7.8 and CMRR is better than 100dB.

In this thesis, a low-power current-mode instrumentation amplifier is proposed for the portable physiological signal recording system. This proposed instrumentation amplifier is used as a front-end amplifier of physiological signal recording system. In general, the physiological signal is very small, for example, the electrocardiogram (ECG) signals. Therefore, the system needs a front-end amplifier to amplify small physiological signals so that it is easier to analyze the signals. Besides, the system will be operated for a longer period because of the proposed amplifier¡¦s low-power property. The circuit theorem, design process and simulation, circuit layout as well as the measurement results all have detailed description in this study. Moreover, a specific physiological signal recording system prototype is proposed. This proposed instrumentation amplifier has used TSMC 0.35 £gm 2P4M CMOS process technology.

The thesis is composed of tow topics: a high performance current-balancing instrumentation amplifier (IA) for ECG (Electrocardiogram) monitoring systems and an IA with CMRR (Common-Mode Rejection Ratio) self-calibration. In the first topic, a high common mode rejection ratio (CMRR) and a low input referred noise instrumentation amplifier (IA) is presented for ECG applications. A high pass filter (HPF) with a small-Gm OTA using a current division technique is employed to attain small transconductance, which needs only a small capacitor in the HPF such that the integration on silicon is highly feasible. The proposed design is carried out by TSMC standard 0.18 £gm CMOS technology. CMRR is found to be 127 dB and the voltage gain is 45 dB according to the simulation results. The second topic discloses an instrumentation amplifier with CMRR self-calibration capability. The propose design is also carried out by TSMC standard 0.18 £gm CMOS technology. To achieve a CMRR of more than 80 dB, a calibration resistance string and a detection circuit have been utilized. The DC gain of the proposed design is 60 dB and the frequency bandwidth is bound in 10 KHz, which is adaptable for biomedical signal acquisition applications.

The thesis is composed of two topics : a low-noise instru-mentation amplifier (IA) for neural signal sensing and a low-power implantable bladder pressure monitor SOC (system-on-chip). A low-noise instrumentation amplifier for bio-medical appli-cations is proposed in the first topic. It is designed for sampling vague neural signals thanks to its high gain, high CMRR in a pre-defined bandwidth. A low-power implantable bladder pressure monitor system is presented in the next topic. The system contains several parts : a commercial pressure sensor, an IA, an analog to digital converter (ADC), a parallel to serial converter (PtoS), an RF transmitter and a sleep controller. The IA with 1-atm canceling is designed for high resolution and linearity in the pre-defined bladder pressure range. For low power and low speed applications, a successive approximation ADC (SA ADC) is employed in the system. A clear flag is added to the PtoS to enhance reliability. Our chip saves a great portion of power to extend the processing time owing to the novel sleep controller.

The first topic of the thesis reveals a mini-invasive low-power measurement system for bladder pressure measurement. Not only can the mode of measurement be selected, the input range and amplification of instrumentation amplifier (IA) is also adjustable. The proposed system can measure the pressure in a bladder in a continuous mode. It also can monitor the pressure in a long-term mode with an automatic sleeping mechanism for power saving. The signal generated by the pressure sensor is sensed by an IA, which is then fed into the following ADC (analog-to-digital converter). The input range of the IA must be adjustable to keep the required linearity. The pressure range of the proposed system is found out to be 5 Psi with the maximum resolution of 1 cm-H2O, which covers the range of all of the known unusual bladder syndromes. The second topic is a self-disable sense technique for content addressable memory (CAM). The differential match-line sense circuit can be self-disabled to choke the charge current fed into the match line right after the comparison result is generated. Besides, the 13-T CAM cell provides the complete write, read, and comparison functions to refresh the data bit and verify its correctness before searching. The average energy consumption of the searching process is 1.872 fJ/bit/search according to thorough simulations.

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Circuits for sampling and retention of analogue signals are commonly implemented with techniques such as switched capacitors (SC). SC circuits employing the storage of charge in a linear capacitor to represent a signal in the form of voltage. Operational Amplifiers (AmpOp's) are used to transfer the load of a capacitor to another, sampling and holding circuits for analogue signals in closed loop. Recently, another technique has been developed without the need of building linear capacitors, making possible projects compatible with VLSI CMOS processes. This technique, called Switched Current (SI), is characterized by processing the signals in the current form, and implemented through the memory retention of electric charge on the gate of a MOS transistor in saturation zone. The charge is hold in a gate-source voltage and hence the current in a transistor. In this model, the excursion of the signal is not directly dependent on the supply voltage, but dependent on the polarization and current signal. This makes the model attractive for low voltage. The technique does not require AmpOp's and capacitors. The speed of the circuit is not limited by AmpOp's and its gainbandwidth product, but by design and manufacturing process. This technique is not yet consolidated and its performance is still not competitive with SC circuits [1] However, SI circuits become interesting as they constitute an open field for future research and the opportunity to be fully implemented in processes manufacturing oriented to purely digital circuits. This work begins with a framework of the subject matter, placing the reader in the state of the art manufacturing technology and some implications that directly affect analog circuits. Are also presented in this section some implementations which serve to characterize what is being done recently in terms of Sigma Delta (ΣΔ) modulators. Abstract vi In Chapter 2, are made a review of sampling and holding bases, the AD conversion techniques with focuses in oversampled AD converters, the circuits that implementing SC and SI modulators and their influences, and finally a review of the nonidealities that involve the practice of project. Chapter 3 a comparative study is done between memory cells SC and SI. Based on a simplified model of small signals, the behavior analyzes on the signal-noise-ratio (SNR), power consumption and speed, providing indications of performance throughout the operating region of MOS transistors. Chapter 4 deals with the initial specifications for the development of a ΣΔ AD converter for a specific implementation. The s tudies and estimates lead to pre-design of the project's ultimate goal the creation of a ΣΔ modulator in the SC and SI techniques. In Chapter 5 is intended to make the measures and tests that establish the standards of comparison, the discussion of results and conclusions. Finally, in Chapter 6, an alternative proposal is presented based on an architecture that performs a sigma-delta modulator with low distortion, implemented with SI circuit. The final conclusions and contributions are presented in Chapter 7. / Circuitos de amostragem e retenção de sinais analógicos são comumente implementados com técnicas de chaveamento de capacitores (Switched Capacitor SC). Circuitos SC empregam o armazenamento de cargas em um capacitor linear para representar um sinal sob a forma de tensão. Amplificadores Operacionais (AmpOp s) são usados para transferir essa carga de um capacitor a outro, amostrando e retendo sinais analógicos em circuitos de malha fechada. Recentemente, uma outra técnica tem sido desenvolvida sem a necessidade de construção de capacitores lineares, tornando possíveis projetos compatíveis com processos de fabricação VLSI CMOS. Esta técnica, chamada de Switched Current (SI), caracteriza-se por processar os sinais sob a forma de correntes, sendo a operação de memorização implementada através da retenção de carga elétrica na porta de um transistor MOS na zona de saturação. A carga retida corresponde a uma tensão portafonte e, conseqüentemente, a uma corrente no transistor. Neste modelo, a excursão do sinal não é diretamente dependente da tensão de alimentação, mas dependente das correntes de polarização e de sinal. Isso torna o modelo atrativo para baixas tensões. A técnica não requer AmpOp s e implementação física de capacitores. A velocidade do circuito não é limitada por AmpOp s e seu produto ganho-banda, mas pelo projeto e processo de fabricação. Essa técnica ainda não está consolidada e sua performance ainda não é competitiva com os circuitos SC [1], Contudo, os circuitos SI tornam-se interessantes na medida em que constituem um campo aberto para futuras pesquisas e pela possibilidade de serem completamente implementados em processos de fabricação voltados a circuitos puramente digitais. Este trabalho inicia com um enquadramento do trabalho proposto, situando o leitor no contexto do estado da arte das tecnologias de fabricação e algumas implicações diretas que afetam circuitos analógicos. São apresentadas ainda nesta seção algumas implementações que servem para caracterizar o que está sendo feito recentemente em termos de conversores tipo Sigma Delta (ΣΔ). No Capítulo 2, faz-se o embasamento sobre as técnicas utilizadas no processo de amostragem e retenção utilizadas para conversão ADΣΔ e uma revisão das não idealidades que envolvem a prática de projeto. No Capítulo 3 é feito um estudo comparativo, entre células de memória SC e SI. Baseado em modelo simplificado de pequenos sinais, analisa-se o comportamento quanto à relação-sinal-ruido (SNR), ao consumo e à velocidade, fornecendo indicações de desempenho em toda região de funcionamento dos transistores MOS. No Capitulo 4 são abordadas as especificações iniciais ao desenvolvimento de um conversor ΣΔ para uma implementação específica. Os estudos e estimativas que conduzem a pré-concepção do projeto têm como objetivo final a geração de um modulador ΣΔ nas técnicas SC e SI. Nos Capítulos 5 efetuam-se as medidas e testes que estabelecem os padrões de comparação, a discussão dos resultados e conclusões. Por fim, no Capítulo 6, uma proposta alternativa é apresentada com base em uma arquitetura de modulador sigma-delta de baixa distorção, implementada em circuito SI. As conclusões e contribuições finais são apresentadas no capítulo 7.

The thesis deals about method of gain signals from strain gauge bridges. There are mentioned some signal conditioning methods for bridges amplifiers and charactered their properties. In the next part of this thesis are calculated the amplifier errors for various temperature. There are projected individual variants of strain gage amplifiers (instrumentation amplifier AD524, isolation amplifier, switched capacitor based instrumentation amplifier), their properties are compared with strain gage amplifier Vishay P-3500.

<p>In modern medicine, the measurement of electrophysiological signals play a key role in health monitoring and diagnostics. Electrical activity originating from our nerve and muscle cells conveys real-time information about our current health state. The two most common and actively used techniques for measuring such signals are electrocardiography (ECG) and electroencephalography (EEG).</p><p>These signals are very weak, reaching from a few millivolts down to tens of microvolts in amplitude, and have the majority of the power located at very low frequencies, from below 1 Hz up to 40 Hz. These characteristics sets very tough requirements on the electrical circuit designs used to measure them. Usually, measurement is performed by attaching electrodes with direct contact to the skin using an adhesive, conductive gel to fixate them. This method requires a clinical environment and is time consuming, tedious and may cause the patient discomfort.</p><p>This thesis investigates another method for such measurements; by using a non-contact, capacitively coupled sensor, many of these shortcomings can be overcome. While this method relieves some problems, it also introduces several design difficulties such as: circuit noise, extremely high input impedance and interference. A capacitively coupled sensor was created using the bottom layer of a printed circuit board (PCB) as a capacitor plate and placing it against the signal source, that acts as the opposite capacitor plate. The PCB solder mask layer and any air in between the two acts as the insulator to create a full capacitor. The signal picked up by this sensor was then amplified by 60 dB with a high input impedance amplifier circuit and further conditioned through filtering.</p><p>Two measurements were made of the same circuit, but with different input impedances; one with 10 MΩ and one with 10 GΩ input impedance. Additional filtering was designed to combat interference from the main power lines at 50 Hz and 150 Hz that was discovered during initial measurements. The circuits were characterized with their transfer functions, and the ability to amplify a very low-level, low frequency input signal. The results of these measurements show that high input impedance is of critical importance for the functionality of the sensor and that an input impedance of 10 GΩ is sufficient to produce a signal-to-noise ratio (SNR) of 9.7 dB after digital filtering with an input signal of 25 μV at 10 Hz.</p>

In modern medicine, the measurement of electrophysiological signals play a key role in health monitoring and diagnostics. Electrical activity originating from our nerve and muscle cells conveys real-time information about our current health state. The two most common and actively used techniques for measuring such signals are electrocardiography (ECG) and electroencephalography (EEG). These signals are very weak, reaching from a few millivolts down to tens of microvolts in amplitude, and have the majority of the power located at very low frequencies, from below 1 Hz up to 40 Hz. These characteristics sets very tough requirements on the electrical circuit designs used to measure them. Usually, measurement is performed by attaching electrodes with direct contact to the skin using an adhesive, conductive gel to fixate them. This method requires a clinical environment and is time consuming, tedious and may cause the patient discomfort. This thesis investigates another method for such measurements; by using a non-contact, capacitively coupled sensor, many of these shortcomings can be overcome. While this method relieves some problems, it also introduces several design difficulties such as: circuit noise, extremely high input impedance and interference. A capacitively coupled sensor was created using the bottom layer of a printed circuit board (PCB) as a capacitor plate and placing it against the signal source, that acts as the opposite capacitor plate. The PCB solder mask layer and any air in between the two acts as the insulator to create a full capacitor. The signal picked up by this sensor was then amplified by 60 dB with a high input impedance amplifier circuit and further conditioned through filtering. Two measurements were made of the same circuit, but with different input impedances; one with 10 MΩ and one with 10 GΩ input impedance. Additional filtering was designed to combat interference from the main power lines at 50 Hz and 150 Hz that was discovered during initial measurements. The circuits were characterized with their transfer functions, and the ability to amplify a very low-level, low frequency input signal. The results of these measurements show that high input impedance is of critical importance for the functionality of the sensor and that an input impedance of 10 GΩ is sufficient to produce a signal-to-noise ratio (SNR) of 9.7 dB after digital filtering with an input signal of 25 μV at 10 Hz.