Ching Lap Sze. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 69-71). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Shuttle Mask --- p.2 / Chapter 1.2 --- Voltage Island --- p.6 / Chapter 1.3 --- Structure of the Thesis --- p.8 / Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- Problem formulation --- p.10 / Chapter 2.2 --- Slicing Floorplan --- p.10 / Chapter 2.3 --- General Floorplan --- p.11 / Chapter 2.3.1 --- Conflict Graph Approaches --- p.11 / Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14 / Chapter 2.4 --- Grid Packing --- p.15 / Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15 / Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17 / Chapter 3 --- Shuttle Mask Floorplanning --- p.18 / Chapter 3.1 --- Problem Description --- p.18 / Chapter 3.2 --- An Overview --- p.20 / Chapter 3.3 --- Modified α-Restricted Grid --- p.21 / Chapter 3.4 --- Branch and Bound Algorithm --- p.23 / Chapter 3.4.1 --- Feasibility Check --- p.25 / Chapter 3.5 --- Dicing Plan --- p.30 / Chapter 3.6 --- Experimental Result --- p.30 / Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36 / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Problem Definition --- p.36 / Chapter 4.2 --- Dynamic Programming --- p.38 / Chapter 4.2.1 --- Problem Definition --- p.38 / Chapter 4.2.2 --- Algorithm Overview --- p.38 / Chapter 4.2.3 --- Size Reduction --- p.39 / Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40 / Chapter 4.3 --- Quad-tree Approach --- p.41 / Chapter 5 --- Voltage Island Partitioning --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Problem Formulation --- p.45 / Chapter 5.3 --- Methodology --- p.46 / Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47 / Chapter 5.3.2 --- Tree Construction --- p.49 / Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50 / Chapter 5.3.4 --- Tree Refinement --- p.52 / Chapter 5.3.5 --- Solution Legalization --- p.53 / Chapter 5.3.6 --- Time Complexity --- p.54 / Chapter 5.4 --- Direct Method --- p.55 / Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56 / Chapter 5.4.2 --- Time Complexity --- p.58 / Chapter 5.5 --- Experimental Results --- p.59 / Chapter 6 --- Conclusion --- p.66 / Bibliography --- p.69

電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸，工作速度和所需功耗的要求，低壓差穩壓器（LDO）在快遞瞬態響應，低噪聲，以及高精度的電子產品中具有廣泛的應用。 / LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓，並使用大電容和電阻通過電容耦合，增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而，電阻電容佔據較大的芯片面積。 / 權衡功耗和芯片尺寸，本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電，以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化，並產生一個電壓脈衝控制迴轉電流，然後通過使用一組數字電路去改變充電或放電的電量。 / 擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量，負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒（傳統）減少到75納秒。 / Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy. / Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components. / By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit. / The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Kwong, Ka Yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract / Acknowledgments / Table of Content / List of Figures / List of Tables / Chapter Chapter 1 --- LDO regulator research background / Introduction / Chapter Section 1.1 --- Generic LDO regulator structure / Chapter Section 1.2 --- Principle of LDO regulator operation / Chapter Section 1.3 --- Specifications / Chapter References / Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators / Introduction / Chapter Section 2.1 --- Slew rate improvement at power transistor gate / Chapter Section 2.2 --- Frequency compensation / Chapter Section 2.3 --- Short summary / References / Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection / Chapter Introduction / Chapter Section 3.1 --- LDO regulator core structure / Chapter Section 3.2 --- Digital switches based LDO regulator / Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit / Chapter Section 3.4 --- Simulation result / Chapter Section 3.5 --- Short summary / References / Chapter Chapter 4 --- Measurement results / Introduction / Chapter Chapter 5 --- Conclusion and Future Work

With Moore’s law grinding to a halt, accelerators are one of the ways that new silicon can improve performance, and they are already a key component in modern datacenters. Accelerators are integrated circuits that implement parts of an application with the objective of higher energy efficiency compared to execution on a standard general purpose CPU. Many accelerators can target any particular workload, generally with a wide range of performance, and costs such as area or power. Exploring these design choices, called Design Space Exploration (DSE), is a crucial step in trying to find the most efficient accelerator design, the one that produces the largest reduction of the total cost of ownership. This work aims to improve this design space exploration phase for accelerators and to avoid pitfalls in the process. This dissertation supports the thesis that early design choices – including the level of specialization – are critical for accelerator development and therefore require benchmarks reflective of production workloads. We present three studies that support this thesis. First, we show how to benchmark datacenter applications by creating a benchmark for large video sharing infrastructures. Then, we present two studies focused on accelerators for analytical query processing. The first is an analysis on the impact of Network on Chip specialization while the second analyses the impact of the level of specialization. The first part of this dissertation introduces vbench: a video transcoding benchmark tailored to the growing video-as-a-service market. Video transcoding is not accurately represented in current computer architecture benchmarks such as SPEC or PARSEC. Despite posing a big computational burden for cloud video providers, such as YouTube and Facebook, it is not included in cloud benchmarks such as CloudSuite. Using vbench, we found that the microarchitectural profile of video transcoding is highly dependent on the input video, that SIMD extensions provide limited benefits, and that commercial hardware transcoders impose tradeoffs that are not ideal for cloud video providers. Our benchmark should spur architectural innovations for this critical workload. This work shows how to benchmark a real world warehouse scale application and the possible pitfalls in case of a mischaracterization. When considering accelerators for the different, but no less important, application of analytical query processing, design space exploration plays a critical role. We analyzed the Q100, a class of accelerators for this application domain, using TPC-H as the reference benchmark. We found that the hardware computational blocks have to be tailored to the requirements of the application, but also the Network on Chip (NoC) can be specialized. We developed an algorithm capable of producing more effective Q100 designs by tailoring the NoC to the communication requirements of the system. Our algorithm is capable of producing designs that are Pareto optimal compared to standard NoC topologies. This shows how NoC specialization is highly effective for accelerators and it should be an integral part of design space exploration for large accelerators’ designs. The third part of this dissertation analyzes the impact of the level of specialization, e.g. using an ASIC or Coarse Grain Reconfigurable Architecture (CGRA) implementation, on an accelerator performance. We developed a CGRA architecture capable of executing SQL query plans. We compare this architecture against Q100, an ASIC that targets the same class of workloads. Despite being less specialized, this programmable architecture shows comparable performance to the Q100 given an area and power budget. Resource usage explains this counterintuitive result, since a well programmed, homogeneous array of resources is able to more effectively harness silicon for the workload at hand. This suggests that a balanced accelerator research portfolio must include alternative programmable architectures – and their software stacks.

Tang Wai Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 40-41). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Algorithms --- p.3 / Chapter 2.1 --- REWIRE --- p.5 / Chapter 2.2 --- RAMFIRE --- p.7 / Chapter 2.3 --- GBAW --- p.8 / Chapter 3 --- FPGA Technology Mapping --- p.11 / Chapter 3.1 --- Problem Definition --- p.13 / Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16 / Chapter 3.2.1 --- FlowMap --- p.16 / Chapter 3.2.2 --- FlowSYN --- p.21 / Chapter 3.2.3 --- CutMap --- p.22 / Chapter 4 --- LUT Minimization by Rewiring --- p.24 / Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27 / Chapter 4.2 --- Experimental Result --- p.28 / Chapter 5 --- Conclusion --- p.38 / Bibliography --- p.40

Tong Ka Yau Dennis. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 77-81). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background on Retiming --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Preliminaries --- p.7 / Chapter 2.3 --- Retiming Problem --- p.9 / Chapter 3 --- Literature Review on Retiming --- p.10 / Chapter 3.1 --- Introduction --- p.10 / Chapter 3.2 --- The First Retiming Paper --- p.11 / Chapter 3.2.1 --- """Retiming Synchronous Circuitry""" --- p.11 / Chapter 3.3 --- Important Extensions of the Basic Retiming Algorithm --- p.14 / Chapter 3.3.1 --- """A Fresh Look at Retiming via Clock Skew Optimization""" --- p.14 / Chapter 3.3.2 --- """An Improved Algorithm for Minimum-Area Retiming""" --- p.16 / Chapter 3.3.3 --- """Efficient Implementation of Retiming""" --- p.17 / Chapter 3.4 --- Retiming in Physical Design Stages --- p.19 / Chapter 3.4.1 --- """Physical Planning with Retiming""" --- p.19 / Chapter 3.4.2 --- """Simultaneous Circuit Partitioning/Clustering with Re- timing for Performance Optimization" --- p.20 / Chapter 3.4.3 --- """Performance Driven Multi-level and Multiway Parti- tioning with Retiming" --- p.22 / Chapter 3.5 --- Retiming with More Sophisticated Timing Models --- p.23 / Chapter 3.5.1 --- """Retiming with Non-zero Clock Skew, Variable Register, and Interconnect Delay""" --- p.23 / Chapter 3.5.2 --- """Placement Driven Retiming with a Coupled Edge Tim- ing Model""" --- p.24 / Chapter 3.6 --- Post-Retiming Register Placement --- p.26 / Chapter 3.6.1 --- """Layout Driven Retiming Using the Coupled Edge Tim- ing Model""" --- p.26 / Chapter 3.6.2 --- """Integrating Logic Retiming and Register Placement""" --- p.27 / Chapter 4 --- Retiming with Gate and Wire Delay [2] --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Problem Formulation --- p.30 / Chapter 4.3 --- Optimal Approach [2] --- p.31 / Chapter 4.3.1 --- Original Mathematical Framework for Retiming --- p.31 / Chapter 4.3.2 --- A Modified Optimal Approach --- p.33 / Chapter 4.4 --- Near-Optimal Fast Approach [2] --- p.37 / Chapter 4.4.1 --- Considering Wire Delay Only --- p.38 / Chapter 4.4.2 --- Considering Both Gate and Wire Delay --- p.42 / Chapter 4.4.3 --- Computational Complexity --- p.43 / Chapter 4.4.4 --- Experimental Results --- p.44 / Chapter 4.5 --- Lin's Optimal Approach [23] --- p.47 / Chapter 4.5.1 --- Theoretical Results --- p.47 / Chapter 4.5.2 --- Algorithm Description --- p.51 / Chapter 4.5.3 --- Computational Complexity --- p.52 / Chapter 4.5.4 --- Experimental Results --- p.52 / Chapter 4.6 --- Summary --- p.54 / Chapter 5 --- Register Insertion in Placement [36] --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.57 / Chapter 5.3 --- Placement of Registers After Retiming --- p.60 / Chapter 5.3.1 --- Topology Finding --- p.60 / Chapter 5.3.2 --- Register Placement --- p.69 / Chapter 5.4 --- Experimental Results --- p.71 / Chapter 5.5 --- Summary --- p.74 / Chapter 6 --- Conclusion --- p.75 / Bibliography --- p.77

So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9

Ng Chong Chon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 100-103). / Abstract in English and Chinese. / 摘要 --- p.iii / Acknowledgments --- p.iv / Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- DMP Architecture --- p.6 / Chapter 2.1 --- Conventional DMP --- p.6 / Chapter 2.1.1 --- Operating Principle --- p.7 / Chapter 2.1.2 --- Disadvantages --- p.10 / Chapter 2.2 --- Pre-processing Clock Architecture --- p.10 / Chapter 2.2.1 --- Operating Principle --- p.11 / Chapter 2.2.2 --- Advantages and Disadvantages --- p.12 / Chapter 2.3 --- Phase-switching Architecture --- p.13 / Chapter 2.3.1 --- Operating Principle --- p.13 / Chapter 2.3.2 --- Advantages and Disadvantages --- p.14 / Chapter 2.4 --- Summary --- p.15 / Chapter Chapter 3 --- Full-Speed Divider Design --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Working Principle --- p.16 / Chapter 3.3 --- Design Issues --- p.18 / Chapter 3.4 --- Device Sizing --- p.19 / Chapter 3.5 --- Layout Considerations --- p.20 / Chapter 3.6 --- Input Sensitivity --- p.22 / Chapter 3.7 --- Modeling --- p.24 / Chapter 3.8 --- Review on Different Divider Designs --- p.28 / Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28 / Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30 / Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32 / Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34 / Chapter 3.9 --- Summary --- p.42 / Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Proposed DMP Topology --- p.46 / Chapter 4.3 --- Circuit Design and Implementation --- p.49 / Chapter 4.4 --- Simulation Results --- p.51 / Chapter 4.5 --- Summary --- p.53 / Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Proposed DMP Topology --- p.56 / Chapter 5.3 --- Circuit Design and Implementation --- p.59 / Chapter 5.3.1 --- Divide-by-4 stage --- p.59 / Chapter 5.3.2 --- TSPC dividers --- p.63 / Chapter 5.3.3 --- Phase-selection Network --- p.63 / Chapter 5.3.4 --- Mode-control Logic --- p.64 / Chapter 5.3.5 --- Duty-cycle Transformer --- p.65 / Chapter 5.3.6 --- Glitch Problem --- p.66 / Chapter 5.3.7 --- Phase-mismatch Problem --- p.70 / Chapter 5.4 --- Simulation Results --- p.70 / Chapter 5.5 --- Summary --- p.74 / Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75 / Chapter 6.1 --- Introduction --- p.75 / Chapter 6.2 --- Proposed DMP Architecture --- p.75 / Chapter 6.3 --- Divide-by-4 Stage --- p.76 / Chapter 6.3.1 --- Current-switch Combining --- p.76 / Chapter 6.3.2 --- Capacitive Load Reduction --- p.77 / Chapter 6.4 --- Simulation Results --- p.81 / Chapter 6.5 --- Summary --- p.83 / Chapter Chapter 7 --- Experimental Results --- p.84 / Chapter 7.1 --- Introduction --- p.84 / Chapter 7.2 --- Equipment Setup --- p.84 / Chapter 7.3 --- Measurement Results --- p.85 / Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85 / Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88 / Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93 / Chapter 7.3 --- Summary --- p.96 / Chapter Chapter 8 --- Conclusions and Future Works --- p.98 / Chapter 8.1 --- Conclusions --- p.98 / Chapter 8.2 --- Future Works --- p.99 / References --- p.100 / Publications --- p.104

The aim of this work is to investigate an algebraic attack on block ciphers called Multiple Right Hand Sides (MRHS). MRHS models a block cipher as a system of n matrix equations Si := Aix = [Li], where each Li can be expressed as a set of its columns bi1, . . . , bisi . The set of solutions Ti of Si is dened as the union of the solutions of Aix = bij , and the set of solutions of the system S1, . . . , Sn is dened as the intersection of T1, . . . , Tn. Our main contribution is a hardware platform which implements a particular algorithm that solves MRHS systems (and hence block ciphers). The case is made that the platform performs several thousand orders of magnitude faster than software, it costs less than US$1,000,000, and that actual times of block cipher breakage can be calculated once it is known how the corresponding software behaves. Options in MRHS are also explored with a view to increase its efficiency. / by Kenneth Matheis. / Thesis (M.S.C.S.)--Florida Atlantic University, 2010. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2010. Mode of access: World Wide Web.

米勒補償是現今最被廣泛使用的頻率補償方法之一。其極點分離現象為雙級放大器供簡易而又可靠的穏定作用。可是，隨着亞微米 CMOS 技術及低電壓電路設計的興起，高增益同時又寬頻寬的放大器設計變得愈來愈困難。雖然多階段方式能實現高增益的放大器規格，但其頻寬會隨之縮窄，頻率補償亦會變得複雜及困難。 / 在過去，很多學術硏究報告都提出了不少方法去解決多階段放大器頻寬縮窄的問題，但這些方法往往離開複雜的頻率補償技巧及電路結構。為了根本性地解決此問題，本論文會提出一個虛擬雙階段放大器的設計。此放大器設計利用了兩個低增益階段來放大進入第二階段前的訊號振幅，從而放進整個放大器的頻寬及增益。由於其簡單的結構，這個設計仍然能夠採用穏定可靠的簡易米勒補償方式來穏定整個放大器。 / 這個設計由CMOS 180nm（互補式屬-氧化層-半導體180納米）技術製成。實驗結果證實了其高增益及寬頻寬的效能。另外，這果放大器亦同時應用在一個低通濾波器的實現上，用以證明其實際應用上的用途。實驗結果證實利用該放大器實現的低通濾波器比用一般雙段放大器的功率消耗減少近 45%。 / Miller compensation is one of the most widely adopted frequency compensation techniques for two-stage amplifier design. With its pole-splitting behavior achieved by connecting a capacitor between the output nodes of the two gain stages, Miller compensation provides a simple and reliable stabilizing function to two stage amplifiers. However, with the advance of sub-micron CMOS technology and low-voltage circuit designs, high-gain and wide-bandwidth amplifier design becomes more difficult. Although multi-stage amplifiers can be used to attain high-gain specification, the bandwidth will be degraded dramatically and the frequency compensation scheme becomes much more complicated. / To solve the problem, several researches have been done to improve the frequency response of multi-stage amplifiers so as to achieve high-gain and wide-bandwidth specifications simultaneously. However, these always result in the increase of circuit complexity and more complicated frequency compensation techniques. / In this thesis, a virtual two-stage Miller compensated amplifier will be proposed. By using two small gain stages, the characteristics of a conventional two-stage Miller compensated amplifier can be retained due to the low output impedance of the two gain stages. The small gain stages boost the input signal amplitude of the second stage such that the generated small-signal output current can be increased significantly. This results in wider signal bandwidth and higher voltage gain. / The proposed design has been fabricated in UMC CMOS 0.18μm technology. Experimental results have verified the concept. From the measurement, the unity-gain frequency of the proposed design is better than the conventional design by 4 times. Moreover, the voltage gain is improved by about 20dB. The current consumption is 124.76μA which is the nearly the same as the conventional design. / In order to show the improvement in real applications, the proposed amplifier has been applied to a fifth-order low-pass filter with corner frequency of 50kHz. Under the same performance, the power consumption of the filter using the proposed amplifier can be reduced by about 45%. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Poon, Hiu Ching. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgments --- p.iv / Table of Content --- p.v / List of Figures --- p.vii / List of Tables --- p.xi / Symbols Declarations --- p.xii / Chapter Chapter 1 --- Background Information / Chapter 1.1 --- High-Gain Amplifier and its Application with Negative Feedback Configuration --- p.1-1 / Chapter 1.2 --- High-Gain Amplifier Design and the Tradeoffs --- p.1-6 / Chapter 1.3 --- High-Gain Amplifier Implementations --- p.1-8 / Chapter 1.4 --- Contribution and Outlines of the Thesis --- p.1-15 / References --- p.1-16 / Chapter Chapter 2 --- Analysis of Frequency Compensation Techniques / Chapter 2.1 --- Simple Miller Compensation --- p.2-1 / Chapter 2.2 --- Miller Compensation with Null Resistor --- p.2-10 / Chapter 2.3 --- Miller Compensation with Multipath Zero Cancellation --- p.2-13 / Chapter 2.4 --- Nested Miller Compensation --- p.2-15 / Chapter 2.5 --- Advanced Frequency Compensation Techniques --- p.2-17 / Chapter 2.6 --- Conclusion of Chapter --- p.2-20 / References --- p.2-22 / Chapter Chapter 3 --- Proposed Amplifier Design / Chapter 3.1 --- Gain Tolerance --- p.3-1 / Chapter 3.2 --- Adjustments on Simple Miller Compensated Two-Stage Amplifier --- p.3-3 / Chapter 3.3 --- Introducing the Small Gain Stage --- p.3-4 / Chapter 3.4 --- Concept of the Proposed Virtual Two-Stage Miller Compensated Amplifier --- p.3-7 / Chapter 3.5 --- Comparisons with Bandwidth Enhanced Miller Compensated Two-Stage Amplifier --- p.3-9 / Chapter 3.6 --- Proposed Virtual Two-Stage Amplifier with Simple Miller Compensation --- p.3-13 / Chapter 3.7 --- Design Considerations and Expected Performance --- p.3-15 / Chapter 3.8 --- Experimental Result --- p.3-18 / Chapter 3.9 --- Conclusions of Chapter --- p.3-31 / References --- p.3-32 / Chapter Chapter 4 --- Implementation of the Low-Pass Filter / Chapter 4.1 --- Implementation of the Low-Pass Filter --- p.4-1 / Chapter 4.2 --- Experimental Result --- p.4-4 / Chapter 4.3 --- Conclusion of Chapter --- p.4-7 / Reference --- p.4-8 / Chapter Chapter 5 --- Conclusion and Future Work / Chapter 5.1 --- Conclusion of Thesis --- p.5-1 / Chapter 5.2 --- Suggestion for Future Work --- p.5-2

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.