Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. Due to this property, KFDDs can provide a more compact representation of the functions than either of the two above-mentioned decision diagrams. The new notion of permuted KFDD is introduced to generate a compact circuit in FPGAs to represent a switching function. A permuted tree search is a free search method which is not limited by the order of variable and the expansion tree as in the cases of KFDD, BDD and FDD. A family of decision diagrams and the theory developed for them are presented in this thesis. The family of permuted Kronecker Functional Decision Diagrams includes BODs and FDDs as subsets is incorporated into program RESPER. Due to this property, permuted KFDD can provide a more compact circuit realization in the multilevel circuit. The circuit obtained can be realized directly with FPGAs like AT 6000 series from Atmel. This algorithm is implemented on several MCNC benchmarks, the results compared with previous programs, TECHMAP and REMIT, are very encouraging. The main achievement of this thesis is the creation of the algorithm which applies a permuted tree search method combined with Davio Expansion and generates Directed Acyclic Graph which is next mapped to a compact circuit realization.

Rapid advancement and innovation in semiconductor research have continuously helped in designing efficient and complex integrated circuits in miniature size. As the device technology, is aggressively scaling to improve the device performance, the issues related to device interconnects, power, and reliability have become a major concern for the designers. These challenges make the design and validation of ASIC extremely complicated. The primary idea of this work is to develop automation tools, to be used in the physical design flows to improve the efficiency of the design flow. The first tool named as variation analysis tool automates the on-chip variation modeling used in the post-layout timing closure phase in the physical design flows. The proposed variation analysis tool models three types of variations such as on-chip variation (OCV), advanced on-chip variation (AOCV) and parametric on-chip variation (POCV). The results of the proposed tool have compared with the Synopsys PrimeTime™ results, and the results show average around 98% accuracy compared to the PrimeTime™. The second tool is for automating repeater analysis in the physical design flows. The repeater automation tool can be used to automate the repeater or buffer insertion process, while technology process is changed from one to another. The tool can calculate the best possible repeater distance for any given metal layer and also, the number of repeaters, combinational or sequential for the user given distance and frequency. The accuracy of this script is compared with the repeater insertion based on the synthesis tools and also, the SPICE simulation.

For many high-speed, high-performance circuits, purely differential inputs are needed. This project focuses on building high-speed voltage converters which can transfer a single-ended signal to a purely differential signal, or a differential input signal to a single-ended signal. Operational transconductance amplifier (OTAs) techniques are widely used in high-speed continuous-time integrated analog signal processing (ASP) circuits because resistors, inductors, integrators, buffers, multipliers and filters can be built by OT As and capacitors. Taking advantage of OT As, very-high-speed voltage converters are designed in CMOS technology. These converters can work in a frequency range from DC (OHz) up to lOOMHz and higher, and keep low distortion over a± 0.5V input range. They can replace transformers so that designing fully integrated differential circuits becomes possible. The designs are based on a MOSIS 2μm n-well process. SPICE simulations of these designs are given. The circuit was laid out with MAGIC layout tools and fabricated through MOSIS. The chip was measured at PSU and Intel circuit labs and the experimental results show the correctness of the designs.

Wireless communication technologies are no longer limited for voice band applications, but have entered the era for multimedia data link. The IEEE802.11 family, which occupies a bandwidth in the multi-mega hertz region with the highest data rate of 54 Mbps, now has become the most widely deployed wireless LAN standards. The rapid adoption of IEEE802.11 for computer wireless networks and their growing popularity in mobile applications highlight the need for a low cost, low power consumption, and monolithic solution. To meet this challenge, traditional RF techniques, which revolved around the superheterodyne architecture can no longer be used. On the contrary, new receiver frontend architectures need to be developed to satisfy the demand of system level integration. Direct downconversion receivers directly translate the RF spectrum to the baseband by setting the LO frequency equal to the RF. Due to the single frequency translation, expensive and bulky off-chip filters and 50 ohm I/O matching networks at IF are no longer required. Also, the single-stage quadrature mixers further simplify the receiver design and reduce the power dissipation. Subsequent baseband components and ADCs are also possible to be integrated with the RF frontend to achieve a monolithic receiver chip. Despite the previously mentioned advantages, the implementation of a direct downconversion receiver has its own set of performance challenges. In particular, the performance is plagued by DC offset, flicker noise, linearity and mismatches etc. The main objective of this project is to investigate the feasibility of using direct downconversion architecture for the IEEE802.11a standard, and implement the design in a 0.18 µm CMOS technology. By approaching the design issue at a theoretic point of view, extensive modeling and simulations based on a SIMULINK IEEE802.11a physical layer theme have been carried out to evaluate the receiver performance. SER results of the receiver demonstrate that the impairments associated with zero IF can be minimised to an acceptable level. Under the guidance of the system level analysis, the circuit level design of a monolithic direct downconversion receiver has been implemented in a 0.18 µm RF CMOS process, including the building blocks of an LNA, mixer, baseband amplifier and a channel-selection filter. Particularly, a novel LNA design methodology with an improved noise figure and less power consumption has been developed. The mixer conversion gain and phase noise have been analysed by a novel approach. The combination topology of the highpass DC offset removal filter and the baseband amplifier provids the best linearity with a negligible noise figure degradation. Circuit simulations are performed using the foundry provided RF design kit with enhanced noise models to capture the extra noise of passive and deep submicron devices. Circuit level simulations show a qualified receiver frontend for the IEEE802.11a standard. As data converters are important building blocks in wireless receivers, research on high performance Sigma-Delta modulators is also included. MATLAB based programs have been developed for both the discrete and continuous time transfer function synthesis. A BPSDM chip with variable centre frequencies has been developed to verify the SDM transfer function algorithm and the design methodology. The design of an ultra fast continuous time SDM is particularly focused on for a broadband data conversion. To alleviate the challenge of the comparator speed limit, a novel noise transfer function with a unit clock delay has been synthesised. With such a delayed transfer function, a three-stage comparator can be acheieved that solves the comparator gain and speed tradeoff. The full chip simulation shows an acceptable performance for the IEEE802.11a standard. / Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2008

Spiral inductors are a key component of mixed-signal and analog integrated circuits (IC's). Such circuits are often fabricated using silicon-based technology, owing to the inherent low-cost and high volume production aspects. However, semiconducting substrate materials such as silicon can have adverse effects on spiral inductor performance due to the lossy nature of the material. Since the operating requirements of many high performance IC's demand reactive components that have high Quality Factor's (Q's), and are thus low loss devices, the need for accurate modeling of such structures over lossy substrate media is key to successful circuit design. The Q's of commonly available off-chip inductors are in the range of 50- 100 for frequencies ranging up to a few gigahertz. Since off-chip inductors must be connected through package pins, solder bumps, etc., which all contribute additional loss and thus lower the apparent Q of an external device, the typical on-chip Q requirement for a given RFIC design is generally lower than that for an off-chip spiral solution. However, a spiral inductor that was designed and fabricated originally in a low loss technology such as thin-film alumina may have substantially worse performance in regard to Q if it is used in a silicon-based technology, owing to the conductive substrate. For this reason, it is imperative that semiconducting substrate effects be accurately accounted for by any modeling effort for monolithic spirals in RFICs. This thesis presents a complete modeling solution for both single and multi-level spiral inductors over lossy silicon substrates, along with design considerations and methods for mitigation of the undesirable performance effects of semiconducting substrates. The modeling solution is based on Spectral Domain Approach (SDA) solutions for frequency dependent complex capacitive (i.e. both capacitance and conductance) parasitic elements combined with a quasi-magnetostatic field solution for calculation of the frequency dependent complex inductive (i.e. both inductance and resistance) terms. The effects of geometry and process variations are considered as well as the incorporation of Patterned Ground Shields (PGS) for the purpose of Q enhancement. Proposals for future extensions of this work are discussed in the concluding chapter. / Graduation date: 2006

In this thesis the network analog method is used to analyze various planar multi-conductor structures in multilayered, lossy dielectric media. The method is based on an efficient impedance network representation of the finite difference approximation of Laplace's equation for the electric potential. Using the network analog method, the transmission line parameters are computed for several different uniform stripline structures in lossless and lossy multilayered dielectric material. The network analog method is also applied to several three-dimensional structures consisting of single and coupled conducting patches of rectangular shape. Results obtained with the network analog method for single conducting patches in single and multilayered lossless dielectric media are in good agreement with published results based on a variational approach. Further results presented in this thesis include the coupling capacitance for coplanar and multilevel patch configurations in lossless and lossy multilayered dielectric media. / Graduation date: 2000

Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are not enough to estimate the power distribution, transistor-level HSPICE simulation to model a microprocessor is too complex and time-consuming. In our research, a VHDL model with enhanced signal tracing function will be developed based on the existing VHDL behavior model. The power consumption of superscalar microprocessor in terms of switching activity and capacitance will be carefully studied. Two factors served as the basis for study: accessibility and importance for power calculations. A brief examination of the datapath suggests that the register file, the instruction cache and data cache are some of the major contributors to power usage. It was therefore decided to track the input and output bit transitions to these modules. These transitions are counted along with the number of accesses to each of the modules. In order to gather all of this data, the original VHDL model simulator has been enhanced. As instructions pass through the CPU, additional code is required to track and record the necessary information. For each individual instruction in the ISA, various information is recorded based on the elements in the processor that the instruction affects. For instance, if the simulator is about to execute a load instruction, the instruction uses the programmer counter, the instruction bus, data bus, the address bus, the ALU (adder) and the register file. The information being recorded for each of these elements must be updated to reflect the execution of that particular load instruction. Also, the inside circuit of each module, i.e. register file, instruction cache and data cache and the 6-transistor memory cell layout considering the 0.25��m CMOS technology will be studied in order to extract the capacitance. We do not need very accurate, absolute power estimation, therefore, we will try to keep the model simple. / Graduation date: 2000

In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters. Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown. / Graduation date: 1999

In recent years, there has been an extensive effort to develop low-cost implementations of radio frequency integrated circuits for consumer applications. This thesis is a research effort in the design and implementation of integrated RF CMOS Power Amplifiers (PAs). A significant challenge in the implementation of RF CMOS ICs is the impact of device, package and passive element parasitics on circuit performance. Passive components are a critical part of any RF IC design, and a process optimized for digital circuits results in inductors and capacitors with very high parasitics. In this work, we have developed a compact model for inductors fabricated in a digital CMOS process. Measured results have been used to further refine the accuracy of the inductor model. This model has been used to predict the impact of inductor parasitics on the performance of RFICs, and is also simple enough to be included in a CAD tool for circuit optimization. We have also studied the operation of Class A, B and C power amplifiers and highlighted design issues which are specific to the implementation of integrated PAs. It is shown that inductor loss has the most critical impact on the performance of integrated PAs. A custom CAD tool, based on the simulated annealing algorithm, has been developed to optimize the performance of power amplifiers for maximum efficiency in the presence of package, device and passive element parasitics. This CAD tool simulates the process of load-pull to determine the optimum large-signal load impedance for the PA, and optimizes the matching network design based on the trade-off between the loss in the matching network and its impedance transformation properties. This trade-off is relevant in the case of high-loss matching networks only, as is the case in integrated RF CMOS ICs. This CAD tool has been used to optimize the efficiency of balanced 100mW CMOS PAs operating at 900MHz. Measured results validate the design and optimization process outlined in this work. It is demonstrated that in the design of RF CMOS ICs, significant benefits can be gained by incorporating parasitics into the design process by means of CAD optimization. The CAD tool developed is an effort towards achieving this goal. It is further proposed that CAD optimization is an essential part of the design of RF CMOS ICs in general, and with the development of improved package, device and passive element models, CAD optimization will replace the "tuning" of RF circuits and result in robust, fully-integrated implementations of RF circuits. / Graduation date: 1999

The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.