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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Prof. Madhavan Swaminathan; Committee Member: Prof. Andrew Peterson; Committee Member: Prof. Sungkyu Lim

Miniaturisation has been the holy grail of mobile technology. The ability to move around with our gadgets, especially the ones for communication and entertainment, has been what semiconductor scientists have battled over the past decades. Miniaturisation brings about reduced consumption in power and ease of mobility. However, the main impediment to untethered mobility of our gadgets has been the lack of unlimited power supply. The battery had filled this gap for some time, but due to the increased functionalities of these mobile gadgets, increasing the battery capacity would increase the weight of the device considerably that it would eventually become too heavy to carry around. Moreover, the fact that these batteries need to be recharged means we are still not completely free of power cords. The advent of low powered micro-controllers and sensors has created a huge industry for more powerful devices that consume a lot less power. These devices have encouraged hardware designers to reduce the power consumption of the gadgets. This has encouraged the idea of wireless power transmission on another level. With lots of radio frequency energy all around us, from our cordless phones to the numerous mobile cell sites there has not been a better time to delve more into research on WPT. This study looks at the feasibilities of WPT in small device applications where very low power is consumed to carry out some important functionality. The work done here compared two rectifying circuits’ efficiencies and ways to improve on the overall efficiencies. The results obtained show that the full wave rectifier would be the better option when designing a WPT system as more power can be drawn from the rectenna. The load also had a great role as this determined the amount of power drawn from the circuitry.

This dissertation focuses on the chemistry, detection, and control of metals and metal contaminants during manufacturing of integrated circuits (ICs) on silicon wafers. Chapter 1 begins with an overview of IC manufacturing, including discussion of the common aqueous cleaning solutions, metallization processes, and analytical techniques that will be investigated in subsequent chapters. Chapter 2 covers initial investigations into the chemistry of the SC2 clean - a mixture of HCl, H2O2, and DI water - especially on the behavior of H2O2 in this solution and the impact of HCl concentration on metal removal from particle addition to silicon oxide surfaces. Chapter 3 includes a more generalized investigation of the chemistry of metal ions in solution and how they react with the silicon oxide surfaces they are brought into contact with, concluding with illumination of the fundamental chemical principles that govern their behavior. Chapter 4 shows how metal contaminants behave on silicon wafers when subjected to the high temperature (≥ 800 °C) thermal cycles that are encountered in IC manufacturing. It demonstrates that knowledge of some fundamental thermodynamic properties of the metals allow accurate prediction of what will happen to a metal during these processes. Chapter 5 covers a very different but related aspect of metal contamination control, which is the effectiveness of metal diffusion barriers (e.g. Ru) in holding a metal of interest, (e.g. Cu), where it is wanted while preventing it from migrating to places where it is not wanted on the silicon wafer. Chapter 6 concludes with an overview of the general chemical principles that have been found to govern the behavior of metals during IC manufacturing processes.

The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems. Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications. While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency. This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies.

This thesis deals with the design, layout, fabrication, testing and characterization of a second-order filter (biquad) using the transconductance-C (gm-C) technique. The biquad was designed to realize the four filter functions - lowpass, highpass, bandpass and notch - by appropriate choice of input and output terminals and element values. The tunable range of frequencies for the biquad was designed to be 18-59MHz. The quality factor of the biquad was designed to be tunable from approximately 1/3 to 3. The filter was designed in LEVEL2 SPICE, laid out using MAGIC, and the circuit was fabricated using MOSIS's 2μm CMOS analog (n-well) process. The circuit board for testing the chip was designed using the PCB design system -PADS-PCB. The chip was tested using the Network Analyzer HP 4195A. The performance of the filter was then compared with the design objectives and simulation results. Both the pole frequency and the quality factor were found to be tunable by the same factor as the design. Noise analysis showed the output noise to be less than -65dB. The notch function could not be experimentally verified due to high sensitivity of this function to component tolerances and process variations. Power dissipation of the filter was found to be 6m W.

Modern three-dimensional integrated circuit design is rapidly evolving to more complex architecture. With continuous downscaling of devices, there is a pressing need for metrology tool development for rapid but efficient process and material characterization. In this dissertation work, application of a novel multiple internal reflection infrared spectroscopy metrology is discussed in various semiconductor fabrication process development. Firstly, chemical bonding structure of thin fluorocarbon polymer film deposited on patterned nanostructures was elucidated. Different functional groups were identified by specific derivatization reactions and model bonding configuration was proposed for the first time. In a continued effort, wet removal of these fluorocarbon polymer was investigated in presence of UV light. Mechanistic hypothesis for UV-assisted enhanced polymer cleaning efficiency was put forward supported by detailed theoretical consideration and experimental evidence. In another endeavor, plasma-induced damage to porous low-dielectric constant interlayer dielectric material was studied. Both qualitative and quantitative analyses of dielectric degradation in terms of increased silanol content and carbon depletion provided directions towards less aggressive plasma etch and strip process development. Infrared spectroscopy metrology was also utilized in surface functionalization evaluation of very thin organic films deposited by wet and dry chemistries. Palladium binding by surface amine groups was examined in plasma-polymerized amorphous hydrocarbon films and in self-assembled aminosilane thin films. Comparison of amine concentration under different deposition conditions guided effective process optimization. A time- and cost-effective method such as current FTIR metrology that provides in-depth chemical information about thin films, surfaces, interfaces and bulk layers can be increasingly valuable as critical dimensions continue to scale down and subtle process variances begin to have a significant impact on device performance.

High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

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