Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance. / VC temporarily stores the victim blocks from level-1 cache to improve cache hits. In addition, MT is used to improve cache replacement performance and VC is used to improve cache hits by supporting stream buffering. We also develop strategies to generate realistic workload by characterizing applications to simulate cache optimization and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, MI, and DFT applications are used to run the simulation programs. Simulation results show that newly introduced Miss Table based cache locking scheme with victim cache significantly improves the predictability and performance/power ratio. In this work, a reduction of 33% in mean delay per task and a reduction of 41% in total power consumption are achieved by using MT and VCs while locking 25% of level-2 cache size in an 4-core system. It is also observed that execution time predictability can be improved by avoiding more than 50% cache misses while locking one-fourth of the cache size. / by Abu Asaduzzaman. / Vita. / Thesis (Ph.D.)--Florida Atlantic University, 2009. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2009. Mode of access: World Wide Web.

Yang, Xiaoqing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 113-120). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

by Siu Hing Kee Stanley. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 87-88). / Abstract --- p.ii / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Background --- p.1-2 / Chapter 1.3 --- Thesis Organization --- p.1-4 / Chapter 2 --- Synthesis of Common Structures in a Microcontroller --- p.2-1 / Chapter 2.1 --- Limitation of Synthesis Tools --- p.2-1 / Chapter 2.2 --- Synthesizable VHDL for Common Structures --- p.2-2 / Chapter 2.2.1 --- Counter --- p.2-3 / Chapter 2.2.2 --- Set-Reset Latch --- p.2-6 / Chapter 2.2.3 --- D Latch --- p.2-9 / Chapter 2.2.4 --- D Flip-flop --- p.2-12 / Chapter 2.2.5 --- Multiplexor --- p.2-13 / Chapter 2.2.6 --- Shift Register --- p.2-15 / Chapter 2.2.7 --- Signal Affected by Two Signal Edges --- p.2-18 / Chapter 2.2.8 --- Combinational Feedback --- p.2-19 / Chapter 2.2.9 --- Short Pulses --- p.2-21 / Chapter 2.2.10 --- Register Transfer Logic --- p.2-22 / Chapter 2.2.11 --- Status Flag --- p.2-26 / Chapter 2.2.12 --- Register Access --- p.2-30 / Chapter 2.2.13 --- Clock Divider --- p.2-34 / Chapter 2.2.14 --- Communication among Processes --- p.2-36 / Chapter 3 --- Synthesis of Components of a Microcontroller --- p.3-1 / Chapter 3.1 --- Timer --- p.3-1 / Chapter 3.2 --- Serial Peripheral Interface (SPI) --- p.3-9 / Chapter 3.3 --- Serial Communication Interface (SCI) --- p.3-16 / Chapter 3.4 --- Parallel I/O Port --- p.3-21 / Chapter 3.5 --- 6805CPU --- p.3-22 / Chapter 3.5.1 --- State Counter --- p.3-23 / Chapter 3.5.2 --- Instruction Decoding and Execution Unit --- p.3-24 / Chapter 3.5.3 --- Interrupt Logic --- p.3-25 / Chapter 3.5.4 --- Instruction Register --- p.3-27 / Chapter 4 --- VHDL Coding and Synthesis --- p.4-1 / Chapter 4.1 --- Controlling Synthesis by VHDL Coding --- p.4-1 / Chapter 4.1.1 --- Structure Control --- p.4-2 / Chapter 4.1.2 --- Feedback Path Control --- p.4-2 / Chapter 4.1.3 --- Control of Use of Storage --- p.4-2 / Chapter 4.1.4 --- Timing Control --- p.4-3 / Chapter 4.2 --- Consequences of the Writing Guidelines --- p.4-5 / Chapter 5 --- Interface Tool for Generation of VHDL for a Microcontroller --- p.5-1 / Chapter 5.1 --- Features --- p.5-1 / Chapter 5.2 --- Construction --- p.5-1 / Chapter 5.3 --- Illustration --- p.5-3 / Chapter 5.4 --- Data Structure --- p.5-5 / Chapter 5.4.1 --- Design List --- p.5-6 / Chapter 5.4.2 --- Instance Data --- p.5-6 / Chapter 5.4.3 --- Instance List --- p.5-8 / Chapter 5.4.4 --- Register Data --- p.5-9 / Chapter 5.4.5 --- Dialogs and Functions --- p.5-10 / Chapter 5.5 --- VHDL Generator for Individual Component --- p.5-11 / Chapter 5.6 --- VHDL Generator for the Whole Microcontroller --- p.5-14 / Chapter 6 --- Conclusion --- p.6-1 / Bibliography --- p.B-1 / Appendix --- p.A-1

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Yeung Wing-ki. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 64-65). / Abstracts in English and Chinese. / Abstracts --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Contents --- p.v / List of Figures --- p.vii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Low ower Design --- p.1 / Chapter 1.2. --- ower Consumtion in Conventional CMOS Logic --- p.2 / Chapter 1.3. --- Adiabatic Switching --- p.7 / Chapter 1.3.1. --- Varying Suly Voltage --- p.7 / Chapter 1.3.2. --- Charge Recovery --- p.12 / Chapter 2. --- Adiabatic Quasi-static CMOS Logic --- p.13 / Chapter 2.1. --- AqsCMOS Logic Building Block --- p.14 / Chapter 2.2. --- AqsCMOS inverter --- p.17 / Chapter 2.3. --- ower Reduced in Sinusoidal Suly --- p.18 / Chapter 2.4. --- Clocking Scheme --- p.21 / Chapter 3. --- Contactless Smart Card --- p.23 / Chapter 3.1. --- Architecture --- p.23 / Chapter 3.2. --- Standardization --- p.26 / Chapter 3.3. --- Universal Asynchronous Receiver and Transmitter (UART) --- p.30 / Chapter 4. --- Clock Recovery --- p.35 / Chapter 4.1 --- Adiabatic Ring Oscillator --- p.35 / Chapter 4.2. --- Secial Frequencies of AqsCMOS Ring Oscillator --- p.39 / Chapter 4.3. --- ower Extraction --- p.41 / Chapter 5. --- Evaluations and Measurement Results --- p.43 / Chapter 5.1. --- Outut Transitions --- p.43 / Chapter 5.2. --- Ring Oscillator --- p.44 / Chapter 5.3. --- Synchronization --- p.47 / Chapter 5.4. --- ower Consumtion --- p.49 / Chapter 6. --- Conclusion --- p.53 / Aendix --- p.54 / Glossary --- p.62 / Reference --- p.64

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented. / Graduation date: 2009

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.