This work demonstrates design of analog circuit blocks using radiation-hardened and temperature tolerant silicon carbide enhancement and depletion JFET. Most of the work to date in silicon carbide is focused on CMOS like circuits, which are less temperature tolerant, compared to JFETs. In this work, efforts have been made to accurately model silicon carbide depletion and enhancement mode n-JFETs. I-V characteristics of the models were simulated for different values of channel thickness and doping concentration. Analog circuit building blocks such as current mirrors and sources are presented for both enhancement mode and depletion mode JFETs at different temperatures. A source coupled differential amplifier was designed using depletion mode silicon carbide n-JFETs. Various differential amplifier specifications such as Voltage swing, input common mode range (ICMR), differential gain, common mode gain and Common mode rejection ratio (CMRR) are simulated at room temperature and at 673K.

A point-of-load converter was designed for a distributed power architecture using a normally off silicon carbide (SiC) junction field effect transistor (JFET) as the enabling technology. The power supply accepts a 208-V single phase input and generates a +26 V and +10 V output for pulsed loads as well as a +5 V and -5 V auxiliary supplies for digital/control circuitry. This work focuses on the integration of the first normally off SiC JFET to allow for an efficient (≥ 93%), high power density (≥ 100 W/in3) power converter demonstrating higher switching frequency. A switching frequency of 500 kHz was achieved which more than doubles the operating frequency of a reference design with silicon MOSFETs. The power supply design described in this thesis integrates a power factor correction pre-regulator with multiple output Weinberg and flyback converters each utilizing normally off SiC JFETs. Experimental results are presented to validate the design.

abstract: Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books. / Dissertation/Thesis / M.S. Electrical Engineering 2011

The objective of this work was to design and develop a high performance field effect transistor to be suitable for monolithic integration with a photodetector for use in long wavelength optical communication systems. It was decided that the most promising type of device for this application was a junction field effect transistor (JFET), fabricated using the alloy In.53Ga.47As grown epitaxially onto an InP substrate. The requirements for such a device were that it should have high transconductance, low input capacitance, and low gate leakage current (for high receiver sensitivity), and that it should have a structure which would be easily integrated monolithically with the desired type of photodetector - an In.53Ga.47As PIN-photodiode. Although this alloy semiconductor has favourable electron transport properties, at the start of this work, high performance field effect transistors had not been realised in this material. In particular, the In.53Ga.47AS FETs that had been made at that time were characterised by low transconductance. Using a device design that incorporated many novel and efficacious features, the JFET described in this work gave results which greatly surpassed all previous (and current) published results of similar devices. This device not only showed high performance, but the novel design features also enabled a simple fabrication scheme. Having developed this very high performance discrete device, the feasibility of monolithic integration with a In.53Ga.47As PIN-photodiode was demonstrated. Although the physical size and material requirements of these two devices were very different, novel design features enabled the construction of a monolithic PIN-FET combination, in which the performance of the JFET was not compromised.

Demand for capable and reliable semiconductor and fabrication technology for high temperature and power electronics applications has been increasing in recent years. Silicon Carbide (SiC), as a wide bandgap compound semiconductor, demonstrates superior characteristics such as high thermal conductivity, high breakdown voltage, and long-lasting reliable operation at elevated temperature. SiC-based circuits and systems are capable to offer significant performance enhancements to various applications. Integrated power management units and conversion modules in HEVs, integrated sensors for aircraft engines, development of small-sized portable power generators are among many applications that require reliable circuits with long-lasting functional lifetime. Nevertheless, there are numerous challenges associated with the design and fabrication of SiC-based circuits. The aim of this research is to practically design and implement novel operational amplifiers (opamps) based on Vertical Channel 4H-SiC JFET (SiC JFET) that can be utilized as sub-circuits of integrated SiC JFET-based circuits and systems. Recently, SiC power JFET-based power management units were developed that deploy non-SiC JFET-based circuits for analog signal processing, driving, and control, because all SiC JFET-based circuits were not available for full integration. However, utilizing SiC JFET for analog design (in order to close the mentioned gap) exhibits significant design challenges, even at room temperature. These fundamental challenges are low intrinsic gain, the requirement to limit the gate to source voltage range, and restrictions on utilizing channel length as a design parameter due to fabrication complexity. These challenges must be successfully overcome at room temperature, before moving towards high temperature SiC JFET-based analog design. The main objective of this dissertation is to establish a design base, overcome the challenges, demonstrate the feasibility, and present all SiC JFET-based opamps that are designed for gain, CMRR, and overall performance. Before attempting to design, both Enhancement and Depletion Mode SiC JFETs are characterized, analyzed, and modeled for simulation. Unique and reliable opamp configurations are presented that take design requirements into account, use threshold voltage instead of channel length as a design parameter, and employ gain enhancement techniques while obtaining maximum possible bandwidth. The final opamps are fabricated and tested and the results show that the objective is accomplished.

Les travaux de cette thèse ont été menés dans le cadre d’une collaboration entre les laboratoires SATIE et LTN IFSTTAR. Ils portent principalement, sur l’étude de la robustesse des composants JFET SiC de puissance pour des applications de découpage à haute fréquence, forte puissance surfacique et à haute température lorsqu’ils sont soumis à des régimes extrêmes de fonctionnement. Les travaux présentés traitent également de façon plus générale l’étude de la durée de vie de packaging dédiés à ce type de composants et adaptés à la haute température pour des applications aéronautiques. La robustesse de différents lots des VJFETs SiC d’un fabricant particulier (SemiSouth) a été étudiée en régimes d’avalanche et de court circuit afin de déterminer les énergies que peuvent supporter ces composants dans ces modes de fonctionnement particuliers en cherchant notamment à quantifier la température du cristal et à mettre en évidence les mécanismes physiques à l’origine des défaillances. Nous avons ainsi également développé un modèle éléments finis thermique afin d’estimer la température de jonction du JFET SiC lors des régimes extrêmes pour chercher à relier l’apparition de la défaillance à la température. Finalement, nous décrivons des mécanismes physiques à l’origine des dégradations lors de la répétition de tels régimes extrêmes de fonctionnement expliquant à terme la destruction par vieillissement des transistors. Un substrat céramique à base de Si3N4 a été le support des études menées dans le cadre de cette thèse sur le packaging. Nous avons caractérisé les dégradations de ces substrats par des analyses acoustiques après vieillissement par cyclage thermique de forte amplitude. Un modèle thermomécanique a été développé afin d’estimer les contraintes mécaniques dans l’assemblage et valider les résultats expérimentaux obtenus. Enfin, nous avons également initiés des travaux de diagnostic thermique sur des puces JFET SiC, par des mesures d’impédance thermique pouvant être utilisées pour la détection de défauts de délaminage dans un assemblage de puissance. / The work presented in this thesis was conducted between SATIE and LTN IFSTTAR laboratories. It focuses on the study of the robustness of SiC power components subjected to hard working conditions for high switching frequency, high power density and high temperature applications. The work also presents a study on the robustness of a dedicated package adapted to high temperature applications. The robustness of several SiC VJFETs from a particular manufacturer (SemiSouth) was studied in avalanche and short circuit modes in order to estimate the energies that can withstand these components in these operating modes. The experimental protocol also includes thermal models to quantify the crystal temperature and to highlight the ageing physical mechanisms causing failure. Therefore, we had developed a finite element model to estimate the thermal junction temperature of the SiC JFET in extreme working conditions to try to relate the failure to the maximum temperature reached after each cycle. Finally, we described the physical mechanisms behind the degradations that explain ultimately the destruction of ageing transistors under repetitive avalanche mode. A ceramic substrate made of Si3N4 has been the support of studies conducted in this thesis on the packaging reliability. We characterized the degradation of these substrates by acoustic analysis after ageing by thermal cycling of high amplitude. A thermo-mechanical model was developed to estimate the mechanical stresses in the assembly and validate the experimental results. Finally, we have initiated thermal diagnostic studies on SiC JFET chips. We have shown that thermal impedance measurements can be used for the detection of delamination defects in a power assembly.

Στην παρούσα διπλωματική εργασία διερευνάται η κατασκευαστική δομή και η λειτουργική συμπεριφορά ημιαγωγικών στοιχείων από καρβίδιο πυριτίου (SiC). Συγκεκριμένα, σε μια πρώτη φάση πραγματοποιείται διεξοδική βιβλιογραφική μελέτη των άρθρων που σχετίζονται με το ημιαγωγικό στοιχείο ισχύος SiC JFET και ειδικότερα η διερεύνηση των ιδιοτήτων του εκείνων που το καθιστούν ανώτερο σε σχέση με άλλα ημιαγωγικά στοιχεία ισχύος από πυρίτιο (Si) ή από SiC, για διακοπτικές εφαρμογές μεγάλης ισχύος και θερμοκρασιών, σύμφωνα με τις τρέχουσες τεχνολογικές εξελίξεις. Σε μια δεύτερη φάση, η διπλωματική εργασία αυτή πραγματεύεται την κατασκευή δύο μετατροπέων ανύψωσης τάσης τύπου boost: ο ένας κατασκευάζεται για βέλτιστη λειτουργία με συμβατικά ημιαγωγικά στοιχεία από πυρίτιο (Si MOSFET και Si pn δίοδος), ενώ ο δεύτερος είναι πανομοιότυπος με τον πρώτο με την ουσιαστική διαφορά ότι τα ημιαγωγικά στοιχεία που χρησιμοποιούνται είναι από καρβίδιο πυριτίου. Πιο συγκεκριμένα χρησιμοποιούνται ένα SiC JFET και μία SiC δίοδος Schottky. Η εργασία αυτή εκπονήθηκε στο Εργαστήριο Ηλεκτρομηχανικής Μετατροπής Ενέργειας του Τμήματος Ηλεκτρολόγων Μηχανικών και Τεχνολογίας Υπολογιστών της Πολυτεχνικής Σχολής του Πανεπιστημίου Πατρών. Αρχικά γίνεται μια μικρή εισαγωγή στις ιδιότητες του SiC ως υλικού προς χρήση για κατασκευή ημιαγωγικών στοιχείων ισχύος και συγκρίνεται με το Si. Επίσης εξάγονται οι λόγοι εκείνοι που, σύμφωνα με τη βιβλιογραφική μελέτη, καθιστούν το JFET ισχύος ως το καταλληλότερο για να κατασκευαστεί από SiC. Στη συνέχεια γίνεται εμβάθυνση στη λειτουργική συμπεριφορά του SiC JFET, δηλαδή μελετώνται τα φαινόμενα που λαμβάνουν χώρα κατά την αγωγή, την αποκοπή και τη μεταβατική του λειτουργία, όπως και η σημασία άλλων ιδιαιτεροτήτων της δομής του που επιδρούν σε αυτήν. Ακολούθως, αποτυπώνονται και μελετώνται 3 βασικές δομές SiC JFET, αναφέρονται τα χαρακτηριστικά τους και επισημαίνονται οι διαφορές τους. Έπειτα, γίνεται αναφορά στην ιδιαιτερότητα των SiC JFET να βρίσκονται σε κατάσταση αγωγής όταν δεν παλμοδοτούνται (normally-on), όπως και στους διακόπτες συνδεσμολογίας σε σειρά (cascode). Στη συνέχεια, καταγράφονται εφαρμογές ισχύος στις οποίες τα SiC JFET βρίσκουν χρήση. Το επόμενο βήμα είναι η κατασκευή των δύο μετατροπέων boost. Πιο συγκεκριμένα τίθενται οι συνθήκες λειτουργίας που καλούνται να εκπληρώσουν, διαστασιολογούνται τα παθητικά στοιχεία τους και σχεδιάζονται τα κυκλώματα ελέγχου και παλμοδότησης της πύλης. Τέλος, γίνονται μετρήσεις στους δύο μετατροπείς και λαμβάνονται αποτελέσματα που αφορούν τις απώλειες και το βαθμό απόδοσης, απ’ τα οποία εξάγονται χαρακτηριστικές καμπύλες για τον κάθε μετατροπέα. / In this diploma thesis, a bibliographical study of the Silicon Carbide (SiC) power JFET's operational behaviour is conducted. The SiC JFET exhibits such operational properties that help to establish it as an advanced power device, in comparison to other Silicon (Si) and SiC power devices. The SiC JFET is a favorable option for high voltage, high power and high temperature switching applications. Once the bibliographical part is conducted, the design and implementation of a 500 W dc/dc boost converter is discussed and analyzed, that employs a SiC VJFET and a SiC Schottky Barrier Diode (SBD. This converter is compared with an identical, more conventional boost converter that uses a Si MOSFET and a Si pn diode, in terms of efficiency and voltage step-up ratio.

The electrical efficiency of telecommunication power supplies is increasing to meet customer demands for lower total cost of ownership. Increased capital cost can now be justified if it enables sufficiently large energy savings, allowing the use of topologies and devices previously considered unnecessarily complex or expensive. Silicon carbide Schottky diodes have already been incorporated into commercial power supplies as expensive, but energy saving components. This thesis pursues the next step of considering silicon carbide transistors for use in telecommunications power converters. A range of silicon carbide transistors was considered with a primary focus on recently developed, normally-off, junction field effect transistors. Tests were devised and performed to uncover a number of previously unpublished characteristics of normally-off silicon carbide JFETs. Specifically, unique reverse conduction and associated gate current draw relationships were measured as well as the ability to block small reverse voltages when a negative gate-source voltage is applied. Reverse recovery-like characteristics were also measured and found to be superior to those of silicon MOSFETs. These characteristics significantly impact the steps that are required to maximize efficiency with normally-off SiC JFETs in circuits where synchronous rectification or bidirectional blocking is performed. A gate drive circuit was proposed that combines a number of recommendations to achieve rapid and efficient switching of normally-off SiC JFETs. Specifically, a low transient output impedance was provided to achieve rapid turn-on and turn-off transitions as well as a high dc output impedance to limit the steady state drive current while sustaining the turned-on state. A prototype circuit was constructed using building blocks that are typically found in single chip MOSFET drivers. The circuit was shown to operate well from a single supply, alleviating the need for a split supply such as that required by many published JFET drive circuits. This demonstrated a proof of concept for a single chip JFET driver solution. An active power factor correction circuit topology was extensively modelled and a prototype designed and tested to verify the model. The circuit was able to operate at switching frequencies in excess of 100kHz when using SiC JFETs, whereas silicon MOSFETs could only achieve switching frequencies of several kHz before switching losses became excessive. The circuit was designed as the dc equivalent for a 2kW, 230V AC input power converter with a split +/-400V dc output. A commercial single phase telecommunications power converter was modified to utilise normally-off SiC JFETs in its power factor correction circuit. The converter was tested and found to achieve similar electrical efficiency with 1200V SiC JFETs to that achieved with 600V silicon MOSFETs. The performance of the 1200V SiC JFETs in this application was also compared to that of 900V silicon MOSFETs and found to be superior. Finally, a prototype three-phase cyclo-converter was modified to use 1200V normallyoff SiC JFETs in place of 600V silicon MOSFETs and found to achieve similar electrical efficiency to the silicon MOSFETs in a 208V three phase system. These results strongly indicate that the 1200V SiC JFETs would provide better performance than 900V silicon MOSFETs in a 400V three phase system (that had been considered for commercial development).

Actuellement, il y a une baisse du prix des ressources énergétiques distribuées, en particulier l'énergie solaire photovoltaïque, conduisant à la croissance significative de leur capacité d'installation dans de nombreux pays. D'autre part, les politiques encourageant l'efficacité énergétique ont favorisé le développement de charges DC dans les zones domestiques, telles que l'éclairage LED, les ordinateurs,, les téléphones, les téléviseurs, les moteurs DC efficaces et les véhicules électriques. Grace à ce changement, le système de distribution de microgrid DC devient plus attractive que le système de distribution à courant alternatif traditionnel. Les avantages principaux du microgrid DC sont l'efficacité énergétique plus élevée, plus facile à intégrer avec les sources d'énergie distribuées et le système de stockage. Alors que de nombreuses recherches se concentrent sur les stratégies de contrôle et la gestion de l'énergie dans le microgrid DC, sa protection reçoit une attention insuffisante et un manque de réglementation et d'expériences. La protection dans les réseaux DC est plus difficile que dans le réseau AC en raison de l'arc continu, de la valeur plus élevée du courant de courtcircuit et du taux de défaut de montée. En outre, dans les réseaux distribués à courant continu sont composés de nombreux dispositifs de commutation électroniques et semi-conducteurs, qui ne supportent le courant de défaut que quelques dizaines de microsecondes. Les disjoncteurs mécaniques, qui ont un temps de réponse de quelques dizaines de millisecondes, ne semblent pas satisfaire aux exigences de sécurité du microréseau à courant continu. L'absence d'un dispositif de protection efficace constitue un obstacle au développement du microgrid DC dans le système distribué. Cette thèse propose un disjoncteur DC auto-alimenté à courant continu utilisant normalement JFET SiC, qui offre un excellent dispositif de protection pour les microgrids DC grâce à son temps de réponse rapide et ses faibles pertes à l'état passant. La conception du disjoncteur DC à semi-conducteurs vise à répondre à deux objectifs: temps de réponse rapide et fiabilité. Les spécifications conçues et les énergies critiques qui entraînent la destruction du disjoncteur sont identifiées sur la base des résultats mesurés d'un JFET populaire dans le commerce. Un pilote de protection très rapide et fiable basé sur une topologie à convertisseur flyback avant est utilisé pour générer une tension négative suffisante pour tourner et maintenir le JFET SiC. Le convertisseur sera activé chaque fois que le disjoncteur détecte des défauts de court-circuit en détectant la tension de drain-source de JFET et crée une tension négative s'applique à la porte de JFET. Pour éviter une défaillance de la porte par surtension au niveau de la grille du JFET, la tension de sortie du convertisseur de retour vers l'avant est régulée à l'aide de la mesure coté primaire. Les résultats expérimentaux sur le prototype du disjoncteur DC ont validé les principes de fonctionnement proposés et ont confirmé que le disjoncteur DC à semi-conducteurs proposé peut interrompre le défaut en 3 μs. D'un autre côté, un modèle du JFET normalement activé dans l'environnement Matlab/Simulink est construit pour étudier les comportements du SSCB pendant une durée de court-circuit. L'accord entre la simulation et les résultats expérimentaux confirment que ce modèle JFET peut être utilisé pour simuler le fonctionnement d'un disjoncteur DC et dans l'étude du fonctionnement du microgrid DC pendant le processus de défaut et de compensation / Currently, there is a drop in the price of distributed energy resources, especially solar PVs, which leads to a significant growth of the installed capacities in many countries. On the other hand, policies encouraging energy efficiency have promoted the development of DC loads in domestic areas, such as LEDs lighting, computers, telephones, televisions, efficient DC motors and electric vehicles. Corresponding to these changes in sources and loads, DC microgrid distribution system becomes more attractive than the traditional AC distribution system. The main advantages of the DC microgrid are higher energy efficiency, easier in integrating with distributed energy sources and storage systems. While many studies concentrate on the control strategies and energy management in the DC microgrid, the protection still receives inadequate attention and lack of regulations and experiences. Protection in DC grids is more complex than AC grids due to the continuous arc, higher short circuit current value and fault rate of rising. Furthermore, the DC distributed grids are composed of many electronic and semiconductor switching devices, which only sustain the fault currents of some tens of microseconds. Mechanical circuit breakers, which have a response time in tens of milliseconds, seem not to meet the safety requirement of DC microgrids. The lack of effective protection devices is a barrier to the development of DC microgrids in the distributed systems. This thesis proposes a self-power solid state DC circuit breaker using normally-on SiC JFET, which offers a great protection device for DC microgrids due to its fast response time and low on-state losses. The design of the solid state DC circuit breaker aims to meet two objectives: fast response time and high reliability. The designed specifications and critical energies that result in the destruction of the circuit breaker are identified on the basis of the experiments of a commercial normally-on JFET. In addition, a very fast and reliable protection driver based on a forward-flyback converter topology is employed to generate a sufficient negative voltage to turn and hold off the SiC JFET. The converter will be activated whenever short-circuit faults are detected by sensing the drain-source voltage, then creating a negative voltage applied to the gate of JFET. To avoid gate failure by overvoltage at the gate of JFET, the output voltage of the forward-flyback converter is regulated using Primary Side Sensing technique. Experimental results validated the working principle of the proposed solid state DC circuit breaker with fault clearing time less than 3 μs. Additionally, a model of the normally-on JFET in Matlab/Simulink environment is built for exploring the behaviors of the solid-state DC circuit breaker during short-circuit faults. The agreement between the simulation and experimental results confirms that this JFET model can be appropriately used for the investigation of solid state DC circuit breaker operations and DC microgrids in general during fault evens and clearing fault processes

A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented.