Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

This dissertation proposes new methods for measuring jitter of high-speed digital signals. The proposed techniques are twofold. First, a low-speed jitter measurement environment is realized by using a jitter expansion sensor. This sensor uses a low-frequency reference signal as compared to high-frequency reference signals required in standard high-speed signal jitter measurement instruments. The jitter expansion sensor generates a low-speed signal at the output, which contains jitter content of the original high-speed digital signal. The low-speed sensor output signal can be easily acquired with a low-speed digitizer and then analyzed for jitter. The proposed low-speed jitter measurement environment using the jitter expansion sensor enhances the reliability of current jitter measurement approaches since low-speed signals used as a reference signal and a sensor output signal can be generated and applied to measurement systems with reduced additive noise. The second approach is direct digitization without using a sensor, in which a high-speed digital signal with jitter is incoherently sub-sampled and then reconstructed in the discrete-time domain by using digital signal reconstruction algorithms. The core idea of this technique is to remove the hardware required in standard sampling-based jitter measurement instruments for time/phase synchronization by adopting incoherent sub-sampling as compared to coherent sub-sampling and to reduce the need for a high-speed digitizer by sub-sampling a periodic signal over its many realizations. In the proposed digitization technique, the signal reconstruction algorithms are used as a substitute for time/phase synchronization hardware. When the reconstructed signal is analyzed for jitter in digital post-processing, a self-reference signal is extracted from the reconstructed signal by using wavelet denoising methods. This digitally generated self-reference signal alleviates the need for external analog reference signals. The self-reference signal is used as a timing reference when timing dislocations of the reconstructed signal are measured in the discrete-time domain. Various types of jitter of the original high-speed reference signals can be estimated using the proposed jitter analysis algorithms.

The quantitative analysis of decomposed electromyographic (EMG) signals reveals information for diagnosing and characterizing neuromuscular disorders. Neuromuscular jitter is an important measure that reflects the stability of the operation of a neuromuscular junction. It is conventionally measured using single fiber electromyographic (SFEMG) techniques. SFEMG techniques require substantial physician dexterity and subject cooperation. Furthermore, SFEMG needles are expensive, and their re-use increases the risk of possible transmission of infectious agents. Using disposable concentric needle (CN) electrodes and automating the measurment of neuromuscular jitter would greatly facilitate the study of neuromuscular disorders. An improved automated jitter measurment system based on the decomposition of CN detected EMG signals is developed and evaluated in this thesis. Neuromuscular jitter is defined as the variability of time intervals between two muscle fiber potentials (MFPs). Given the candidate motor unit potentials (MUPs) of a decomposed EMG signal, which is represented by a motor unit potential train (MUPT), the automated jitter measurement system designed in this thesis can be summarized as a three-step procedure: 1) identify isolated motor unit potentials in a MUPT, 2) detect the significant MFPs of each isolated MUP, 3) track significant MFPs generated by the same muscle fiber across all isolated MUPs, select typical MFP pairs, and calculate jitter. In Step one, a minimal spanning tree-based 2-phase clustering algorithm was developed for identifying isolated MUPs in a train. For the second step, a pattern recognition system was designed to classify detected MFP peaks. At last, the neuromuscular jitter is calculated based on the tracked and selected MFP pairs in the third step. These three steps were simulated and evaluated using synthetic EMG signals independently, and the whole system is preliminary implemented and evaluated using a small simulated data base. Compared to previous work in this area, the algorithms in this thesis showed better performance and great robustness across a variety of EMG signals, so that they can be applied widely to similar scenarios. The whole system developed in this thesis can be implemented in a large EMG signal decomposition system and validated using real data.

The quantitative analysis of decomposed electromyographic (EMG) signals reveals information for diagnosing and characterizing neuromuscular disorders. Neuromuscular jitter is an important measure that reflects the stability of the operation of a neuromuscular junction. It is conventionally measured using single fiber electromyographic (SFEMG) techniques. SFEMG techniques require substantial physician dexterity and subject cooperation. Furthermore, SFEMG needles are expensive, and their re-use increases the risk of possible transmission of infectious agents. Using disposable concentric needle (CN) electrodes and automating the measurment of neuromuscular jitter would greatly facilitate the study of neuromuscular disorders. An improved automated jitter measurment system based on the decomposition of CN detected EMG signals is developed and evaluated in this thesis. Neuromuscular jitter is defined as the variability of time intervals between two muscle fiber potentials (MFPs). Given the candidate motor unit potentials (MUPs) of a decomposed EMG signal, which is represented by a motor unit potential train (MUPT), the automated jitter measurement system designed in this thesis can be summarized as a three-step procedure: 1) identify isolated motor unit potentials in a MUPT, 2) detect the significant MFPs of each isolated MUP, 3) track significant MFPs generated by the same muscle fiber across all isolated MUPs, select typical MFP pairs, and calculate jitter. In Step one, a minimal spanning tree-based 2-phase clustering algorithm was developed for identifying isolated MUPs in a train. For the second step, a pattern recognition system was designed to classify detected MFP peaks. At last, the neuromuscular jitter is calculated based on the tracked and selected MFP pairs in the third step. These three steps were simulated and evaluated using synthetic EMG signals independently, and the whole system is preliminary implemented and evaluated using a small simulated data base. Compared to previous work in this area, the algorithms in this thesis showed better performance and great robustness across a variety of EMG signals, so that they can be applied widely to similar scenarios. The whole system developed in this thesis can be implemented in a large EMG signal decomposition system and validated using real data.

Most modern clock and data recovery circuits (CDR) are based on analog blocks that need to be redesigned whenever the technology process is to be changed. On the other hand, CDR based blind oversampling architecture (BO-CDR) can be completely designed in a digital process which makes its migration very simple. The main disadvantages of the BO-CDR that are usually mentioned in a literature are complexity of its digital circuitry and finite phase resolution resulting in larger jitter sensitivity and higher error rate. This thesis will show that those problems can be solved by designing a new algorithm of BO-CDR and subsequent optimization. For this task an FPGA was selected as simulation and verification platform. This enables to change parameters of the optimized circuit in real time while measuring on real links (unlike a simulation using inaccurate link models). The output of this optimization is a new BO-CDR algorithm with heavily reduced complexity and very low error rate. A new FPGA-based method of jitter measurement was developed (primary for CDR analysis), which enables a quick link characterization without using probing or additional equipment. The new method requires only a minimum usage of FPGA resources. Finally, new measurement equipment was developed to measure bit error distribution on FSO links to be able to develop a suitable error correction scheme based on ARQ protocol.