Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

Master of Science / Department of Electrical and Computer Engineering / William Kuhn / Studies of Silicon-on-Sapphire (SOS) CMOS device operation in cryogenic environments are presented. The main focus was to observe the characteristic changes in high, medium and low threshold SOS NFETs as well as SOS silicide blocked (SN) resistors when the operational temperature is in the devices’ freeze-out range below 77 Kelvin. The measurements taken will be useful to any integrated circuit (IC) designer creating devices based on an SOS process intended to operate in cryogenic environments such as superconducting electronics and planetary probes. First, a 1N4001 rectifier and a 2N7000 NFET were tested to see how freeze-out effects standard diode and MOS devices. These devices were tested to see if the measurement setup could induce carrier freeze-out. Next, SOS devices were studied. Data was collected at room temperature and as low as 5 Kelvin to observe resistance changes in an SN resistor and kink effect, threshold voltage shifts and current level changes in transistors. A 2μm high threshold NFET was tested at room temperature, 50 Kelvin, 30 Kelvin and 5 Kelvin to observe effects on I-V curves at different temperatures with-in the freeze-out range. A 2μm medium threshold NFET was tested down to 56 Kelvin to see if the behavior is similar to the high threshold FET. A 2μm intrinsic, or low threshold, NFET was also tested with the assumption it would be the most susceptible to carrier freeze-out. All of the devices were found to behave well with only mild effects noted.

In this thesis, a bottom gate TFT with smart body tie device is realized, For a PDSOI devices, which usually uses large layout areas of body ties, and it has self-heating effect resulting from the buried oxide between the silicon film and substrate, which has a lower thermal conductivity. In order to suppress the short channel effect and reduce leakage current, we dug out in advance the PN junction to formed the ultra thin film body, besides, in order to reduce Miller's capacitance effect we formed enough thickness of spacer at both sides of the bottom gate and let the source and the drain region do not too closer nearly. According to the simulation results of ISE TCAD, the TFT with smart body tie device can alleviate self-heating effect and can achieve kink-free at output characteristic curve due to hot carriers by impact ionization and enhance the breakdown voltage of the device. Although the drive current of the TFT device lower than conventional TFT due to the parasitic resistance in the body region, the output characteristic curve is smooth in the saturation zone; the device suppress the short channel effect and improve the performance of the device due to most areas of PN junction are dug out.

As Si-manufacturing compatible SiGe HBTs are making rapid in-roads into RF through mm-wave circuit applications, with performance levels steadily marching upward, the use of these devices under extreme environment conditions are being studied extensively. In this work, test structures of SiGe HBTs were designed and put into extremely low temperatures, and a new negative differential resistance effect and a novel collector current kink effect are investigated in the cryogenically-operated SiGe HBTs. Theory based on an enhanced positive feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector current, indirectly producing both phenomena. This theory is confirmed using calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high-injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. Circuit implication is discussed.