In this paper, we propose a novel thin film MOSFET with source/drain tie and discontinuously block oxide layers. Improving process is very important, when the gate length of SOI MOSFET is reduced. To overcome the misalignment problem, we use self-aligned technology to fabricate this device. In addition, the device has discontinuously block oxide layers; they can improve short channel effects, reduce the parasitic capacitance, and decrease the leakage current cause by P-N junction between source/drain and body regions. They also supply two pass ways to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, these two pass ways can be seen as the parallel equivalent resistance results in a reduced series resistance and an increased drain saturation current. According to the ISE TCAD 10.0 simulation results, the discontinuously block oxide layers can not only improve the short channel effects, but also eliminate the floating-body effect and diminish the self-heating effect because of the pass ways.

In this thesis, a bottom gate TFT with smart body tie device is realized, For a PDSOI devices, which usually uses large layout areas of body ties, and it has self-heating effect resulting from the buried oxide between the silicon film and substrate, which has a lower thermal conductivity. In order to suppress the short channel effect and reduce leakage current, we dug out in advance the PN junction to formed the ultra thin film body, besides, in order to reduce Miller's capacitance effect we formed enough thickness of spacer at both sides of the bottom gate and let the source and the drain region do not too closer nearly. According to the simulation results of ISE TCAD, the TFT with smart body tie device can alleviate self-heating effect and can achieve kink-free at output characteristic curve due to hot carriers by impact ionization and enhance the breakdown voltage of the device. Although the drive current of the TFT device lower than conventional TFT due to the parasitic resistance in the body region, the output characteristic curve is smooth in the saturation zone; the device suppress the short channel effect and improve the performance of the device due to most areas of PN junction are dug out.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

This paper investigates the device behavior of a novel pseudo tri-gate ultrathin channel vertical MOSFET with source/drain tie (S/D tie), the PTG-SDT VMOS. The S/D tie (SDT) of this novel device circumvents short channel effect (SCEs). A double- surround-gate (the mid-gate and the spacer gate) is also presented to investigate the effect of S/D tie. According to the 2D simulation, three kinds of pseudo vertical MOSFETs are now proposed. The first one is to investigate the device characteristics of the new PTG-SDT VMOS. Our proposed structure also mitigates self-heating effect (SHEs), thereby enhancing the drain drive current and the thermal stability. Owing to its ultrathin channel (Tsi = 10 nm), the PTG-SDT VMOS has a very low subthreshold swing of 60 mV/dec, for channel lengths from 90 nm down to 40 nm. It is also found to control drain-induced barrier lowing (DIBL) and to have an excellent Gm of 4.5 mS/£gm at the channel length 40 nm. The second one, we proposed the ultrathin channel pseudo tri-gate vertical MOSFET with natural source/drain tie (NSDT), the big source/drain tie (BSDT), the SDT and the without source/drain tie (WSDT) VMOS. The PTG VMOS of this novel structure circumvents short channel effects (SCEs). A new natural S/D tie (N-SDT) is also presented to investigate of the PTG VMOS. According to 2D simulation, the PTG-NSDT also show the excellent thermal dissipated such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 47% and 66% respectively, thereby enhancing the ON-state and OFF-state current ratio. In addition, the dependence of GIDL current on body bias and temperature is characterized and discussed when the source and drain interchanged. Although the PTG VMOS keep the double-surround-gate and S/D tie structure, the design flow is more simplify even increase the drain drive current and immunity the SHEs.

This thesis is mainly proposed and discussed the characteristics of polycrystalline silicon thin film transistor putting forward and probing into four kinds of novel buried-oxide structures. Because of the shortcoming of the traditional polycrystalline silicon thin film transistor, like leakage current (On/Off state current), subthreshold swing, floating body effect (kink effect), self-heating effect, and short channel effect etc.. Thus, we propose and fabricate four kinds of novel structural polycrystalline silicon thin film transistors that are involved in the following, indicating to improve the critical issues of polycrystalline silicon thin film transistor mentioned above. 1. We propose and fabricate the multiple/dual trenched-body polycrystalline silicon thin film transistor. This proposed structure is demonstrated to obviously suppress the off-state leakage up to 70% reduction, comparing with the conventional device. Also, we survey the reliability of this proposed device included temperature and DC hot-carrier stress effects. We found that the trenched-body TFTs perform more rapid degradation than the conventional TFT does after the temperature and stress durations, but their electrical characteristics are still superior to the conventional counterparts. Importantly, we demonstrate that this proposed device have a dramatic potential to be a novel capacitorless 1T-DRAM, because of its large floating-body-charge storages. As the experiment, the large threshold voltage shift is examined apparently after a certain write and erase operations, leading to a manifest programming window. 2. We propose and fabricate the block-oxide polycrystalline silicon thin film transistor. This proposed structure can not only improve the leakage issue of conventional device seriously, but also avoid fluctuating threshold voltage attributed from the ultra-thin film effect. 3. We propose and fabricate the floating-body contact polycrystalline silicon thin film transistor. This structure is modified by the conventional contact window in order to effectively improve the kink effect, utilizing the bottom gate polycrystalline silicon thin film transistor. 4. Finally, we propose and simulate the non-continuous buried layer polycrystalline silicon thin film transistor. This structure built upon the field oxidation layer can effectively improve the self-heating effect and kink effect. Furthermore, this structure is simple to fabricate, practical, and completely compatible on CMOS technology.

abstract: Combining the rapid development of semiconductor technologies, miniaturization of integrated circuits (ICs), and scaling down the device size is trending towards faster, cheaper, and more reliable components for low-power integrated circuits. Most research and development relate to efficiency, structure, materials, and performance. However, the thermal problem is also created and becomes more critical with shrinking device dimensions and increased integration densities, such that it affects the device performance and leads to degradation and damage. At the nanometer scale, the self-heating effect (SHE) is one of the main factors to degrade devices. Therefore, tracking and quantifying the SHE is important for reliability and efficiency issues. In this dissertation, engineers design two identical and closely spaced 40nm gate length silicon-on-insulator (SOI) n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) that share a common source with the same active silicon region. One of the MOSFETs acts as a heater to heat-up the active region, while the other one is a thermometer to evaluate the SHE and local temperature changes. The thermometer provides a method to calibrate the numerical models of self-heating and track the heat flow. Moreover, it also involves a trap-rich SOI wafer technology, in which a trap-rich layer, with higher resistivity and lower thermal conductivity compared to conventional bulk silicon substrates. The trap-rich SOI substrates can reduce the cross-talk and minimize the power consumption to increase the system performance. In particular, it offers a solution to radio frequency integrated circuits (RFICs) which require fast switching and low leakage. In high power amplifier (PA) applications, Watt-level PAs operates at less than 50% efficiency because of temperature limitations. The author uses experimental measurements of the local temperature changes, combined with simulations to examine the heat flow and temperature distribution. The approach may be useful to build a self-test application, because it can quantify the temperature changes by putting one or multiple NMOSFET thermometers around a complementary metal-oxide-semiconductor (CMOS) power amplifier, while only adding minimum die area. It points to ways in which it can optimize the reliability of RFIC applications, which operate under high-temperature or high-power conditions to protect the device before it is overheated or damaged. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

<p>As the miniaturization of the transistors in integrated circuits approaches the atomic scale limit, novel materials with exceptional performance are desired. Moreover, to conduct enough current with an ultrathin and small-scale body, high drain current density is preferably required. Nevertheless, devices may suffer seriously from self-heating effect (SHE) with high drain bias and current if the generated heat cannot be dissipated efficiently. In this thesis, we introduce two material systems and several techniques to accomplish the demand without SHE. Tellurium, as a van der Waals material composed by atomic helical chains, is able to realize its one-dimensional structure. We illustrate that the cross-sectional current density of 150 MA/cm2 is achieved through boron nitride nanotube (BNNT) encapsulation without SHE due to the superior thermal conductivity of BN. With the nanotube encapsulation technique applied, one-dimensional tellurium nanowire transistors with diameter down to 2 nm are realized as well, and single tellurium atomic chain is isolated. Furthermore, atomic-layer-deposited indium oxide (In2O3) as thin-film transistors exhibit even better current carrying capacity. Through co-optimization of their electrical and thermal performance, drain current up to 4.3 mA/μm is achieved with a 1.9-nm-thick body without SHE. The alleviation of SHE is due to a) the high thermal conductivity of the substrate assisting on efficiently dissipating the generated thermal energy, b) SHE avoidance with short-pulse measurement, and c) interface engineering between the channel stack and the substrate. These two material systems may be the solid solution to the desire of high current density transistors in the post-Moore era.</p>

<p>Beta-gallium oxide (<i>β</i>-Ga₂O₃) is an emerging wide bandgap semiconductor for next generation power devices which offers the potential to replace GaN and SiC. It has an ultra-wide bandgap (UWBG) of 4.8 eV and a corresponding <i>E</i>_brof 8 MV/cm. <i>β</i>-Ga₂O₃also possesses a decent intrinsic electron mobility limit of 250 cm²/V<i>·</i>s, yielding high Baliga’s figure of merit of 3444. In addition, the large bandgap of <i>β</i>-Ga₂O₃gives stability in harsh environment operation at high temperatures. </p> <p>Although low-cost large-size <i>β</i>-Ga₂O₃native bulk substrates can be realized by melt growth methods, the unique property that (100) surface of <i>β</i>-Ga₂O₃has a large lattice constant of 12.23 Å allows it to be cleaved easily into thin and long nano-membranes. Therefore, <i>β</i>-Ga₂O₃FETs on foreign substrates by transferring can be fabricated and investigated before <i>β</i>-Ga₂O₃epitaxy technology becomes mature and economical viable. Moreover, integrating <i>β</i>-Ga₂O₃on high thermal conductivity materials has an advantage in terms of suppressing self-heating effects. </p><p>In this dissertation, structural and material innovations to overcome and improve critical challenges are summarized as follows: 1) Top-gate nano-membrane <i>β</i>-Ga₂O₃FETs on a high thermal conductivity diamond substrate with record high maximum drain current densities are demonstrated. The reduced self-heating effect due to high thermal conductivity of the substrate was verified by thermoreflectance measurement. 2) Local electro-thermal effect by electrical bias was applied to enhance the electrical performance of devices and improvements of electrical properties were shown after the annealing. 3) Thin thermal bridge materials such as HfO₂and ZrO₂were inserted between <i>β</i>-Ga₂O₃and a sapphire substrate to reduce self heating effects without using a diamond substrate. The improved thermal performance of the device was analyzed by phonon density of states plots of <i>β</i>-Ga₂O₃and the thin film materials. 4) Nano-membrane tri-gate <i>β</i>-Ga₂O₃FETs on SiO₂/Si substrate fabricated via exfoliation have been demonstrated for the first time. 5) Using the robustness of <i>β</i>-Ga₂O₃in harsh environments, <i>β</i>-Ga₂O₃ferroelectric FETs operating as synaptic devices up to 400 °C were demonstrated. The result offers the potential to use the novel device for ultra-wide bandgap logic applications, specifically neuromorphic computing exposed to harsh environments.<br></p>