O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

Esta dissertação apresenta o projeto de um amplificador de baixo ruído (LNA) para aplicação em 2,4 GHz na tecnologia CMOS 0,35 µm. A metodologia baseia-se na obtenção das dimensões dos dispositivos do circuito considerando o consumo de potência e o desempenho em relação ao ruído. Os resultados mostram que a metodologia implementada é eficaz no projeto de um LNA quando se comparam os resultados obtidos nos cálculos com os resultados obtidos no simulador. A expressão de corrente que considera canal curto impõe maior precisão nos resultados, pois se aplica o ajuste de curva com a curva de corrente obtida pelo simulador. Isto permite maior precisão nos resultados dos cálculos de ruído. O fluxo do projeto baseia-se na implementação de dispositivos ideais obtidos de projeto com o propósito de fazer-se comparações dos resultados de cálculos com as simulações, então, usa-se dispositivos reais e ajusta-se o circuito para encontrar melhores desempenhos quanto às especificações. Os resultados mostram a necessidade de ajuste do circuito quando inserido o modelo do indutor para que se consiga desempenhos próximos dos obtidos inicialmente. Em seguida, realiza-se o layout do circuito e sua extração parasitária para fins de fabricação. Verifica-se que a metodologia apresentada é capaz de direcionar a um projeto de um LNA na tecnologia com resultados finais satisfatórios de ganho, ruído e consumo. Assim os resultados esperados são 14,66 dB de ganho, 1,9 dB de fator de ruído e 2,99 mA de consumo de corrente (9,87 mW em 3,3 V de alimentação) ambos no primeiro estágio. / This work presents the design of a low-noise amplifier (LNA) for application at 2.4 GHz using CMOS 0.35 µm technology. The methodology is based on obtaining the dimensions of the devices taking into account of power consumption and performance on noise. Results show that the implemented methodology is efficient in the design of LNAs when it compares results obtained by calculation and simulation. The expression of current that considers short-channel effects increases the precision of results because curve fitting is applied with the current of the simulator. This permits precision on the results of the noise calculation. The design-flow firstly bases on implementation of ideal devices obtained by design on purposes of doing comparisons between calculated and simulated results, then real devices is used and the circuit is fixed to find better performance regarding the specifications. The results showed the necessity of adjusts in the circuit when the inductor is inserted to reach a closer initial performance. Afterwards, the layout of the circuit and its parasitic extraction are worked out for purposes of fabrication. It is verified that this methodology is capable of directing to the design of LNAs using the proposed technology with satisfactory final results of gain, noise and power consumption. Therefore, the expected results are 14,66 dB of gain, 1,9 dB of noise figure, 2,99 mA of current consumption (9,87 mW within 3.3 V of supply voltage) both of them at first stage.

Abstract The focus of this thesis is Ultra Wideband (UWB) Impulse Radio (UWB-IR) transmitters and non-coherent receivers. The aim of the thesis is to investigate, analyze and design UWB-IR transmitter and receiver structures both from a theoretical and circuit design viewpoint. An UWB-IR transmitter structure is proposed and is the subject of a detailed investigation. The transmitter generates a Gaussian monocycle and can be modified to generate a family of Gaussian waveforms. The Gaussian monocycle is easy to generate while providing good bit-error-rate (BER) performance. The Gaussian monocycle has a wide -10 dB bandwidth and a zero-DC component which does not decrease antenna efficiency. The transmitter design includes a delay locked loop (DLL) based frequency synthesis approach. The advantage of using a frequency synthesis approach based on a DLL is based on the fact that a DLL generates less noise than a phase locked loop (PLL) and is inherently stable. The generated pulse has a width of less than 350 ps and a -10 dB bandwidth of 4.7 GHz. The power consumption of the designed UWBIR transmitter is 20 mW at a voltage supply of 3.3 V. Compared with other integrated UWB-IR transmitters, the transmitter presented in this thesis has the lowest pulse width for comparable integrated processes, one of the lower power consumptions and a low die area. The BER performance of several UWB-IR non-coherent receiver structures is presented. The energy detection (ED) receiver offers the same BER performance as the transmitted reference scheme with binary pulse amplitude modulation (BPAM) but has a lower implementation complexity since it does not require an analogue delay line in its structure. Circuit performance of several blocks of the ED receiver is presented. The radio frequency (RF) front-end and analogue baseband sections of the receiver have been designed as an integrated circuit (IC) in a 0.35 μm bipolar complementary metal oxide semiconductor (BiCMOS) process. The RF front-end section includes a low noise amplifier (LNA), a variable gain amplifier (VGA) and a Gilbert cell. The LNA has a noise figure (NF) of less than 3 dB, a gain of 18 dB in the interest bandwidth and less than 20 mW of power consumption. The NF of the LNA can be reduced even further at the expense of a higher power consumption or by using input pads with lower capacitance values. The noise figure can be also lowered by using a process which provides transistors with higher transit frequency (fT). Trading-off power consumption for noise is still a key design issue in the design of integrated UWB-IR receivers. The analogue baseband section includes a bank of integrators and a 4-bit analogue to digital converter (ADC). The ADC is running at a sampling rate equal to the symbol rate and takes only 2 mW of power at 3.3 V supply. The power consumption of the designed integrated front-end and analogue baseband receiver sections is 117 mW at a power supply of 3.3 V. The digital baseband of the receiver have been implemented on a field programmable gate array (FPGA) technology. The power consumption of the baseband is 450 mW with a power supply of 1.2 V and a maximum supply of 3.3 V for input-output pins. The total power consumption of the designed transceiver is 587 mW. When compared with other UWB receiver architectures, the energy detection receiver has the lowest power consumption due to the low power consumption of the LNA, simple synchronization architecture and low sampling rate of the ADC.

This Master's Thesis deals with a design of L-band receiver front-end. In the concrete the receiver is designed for receiving signals of frequency band 1,3 GHz. All particular blocks from low noise amplifier to intermediate frequency amplifier and frequency doubler in LO input are described, designed and simulated in program Ansoft. The part of this Master's Thesis is aimed to construct a working front-end receiver and to measure its basic parameters.

This master's thesis is engage in suggestion of low noise 70 cm band amplifier with filter and diode attenuator. At first the thesis describes the basic parameters of amplifier, for example gain, noise figure and dynamic extent. Later in detail describes individual parts, which are the device consist of. At every part of system is mentioned the diagram of connection and values of components, which are ascertained from calculation, simulation and recommendation of producer. The characteristic parameters of amplifier were measured after construction.

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.

Gallium Nitride (GaN) technology is capable of very high power levels but suffers from high non-linearity. With the advent of 5G technologies, high linearity is in greater demand due to complex modulation schemes and crowded RF (Radio Frequency) spectrum. Because of the non-linearity issue, GaN power amplifiers have to be operated at back-off input power levels. Operating at back-off reduces the efficiency of the power amplifier along-with the output power. This research presents a technique to linearize GaN amplifiers. The linearity can be improved by splitting a large device into multiple smaller devices and biasing them individually. This leads to the cancellation of the IMD3 (Third-order Intermodulation Distortion) components at the output of the FETs and hence higher linearity performance. This technique has been demonstrated in Silicon technology but has not been previously implemented in GaN. This research work presents for the first time the implementation of this technique in GaN Technology. By the application of this technique, improvement in IMD3 of 4 dBc has been shown for a 0.8-1.0 GHz PA (Power Amplifier), and 9.5 dBm in OIP3 (Third-order Intercept Point) for an S-Band GaN LNA, with linearity FOM (IP3/DC power) reaching up to 20. Large-signal simulation and analysis have been done to demonstrate linearity improvement for two parallel and four parallel FETs. A simulation methodology has been discussed in detail using commercial CAD software. A power sampler element is used to compute the IMD3 currents coming out of various FETs due to various bias currents. Simulation results show by biasing one device in Class AB and others in deep Class AB, IMD3 components of parallel FETs can be made out of phase of each other, leading to cancellation and improvement in linearity. Improvement up to 20 dBc in IMD3 has been reported through large-signal simulation when four parallel FETs with optimum bias were used. This technique has also been demonstrated in simulation for an X-Band MMIC PA from 8-10 GHz in GaN technology. Improvements up to 25-30 dBc were shown using the technique of biasing one device with Class AB and other with deep class AB/class B. The proposed amplifier achieves broadband linearization over the entire frequency compared to state-of-the-art PA's. The linearization technique demonstrated is simple, straight forward, and low cost to implement. No additional circuitry is needed. This technique finds its application in high dynamic range RF amplifier circuits for communications and sensing applications. / Doctor of Philosophy / Power amplifiers (PAs) and Low Noise Amplifiers (LNAs) form the front end of the Radio Frequency (RF) transceiver systems. With the advent of complex modulation schemes, it is becoming imperative to improve their linearity. Through this dissertation, we propose a technique for improving the linearity of amplifier circuits used for communication systems. Meanwhile, Gallium Nitride (GaN) is becoming a technology of choice for high-power amplifier circuits due to its higher power handling capability and higher breakdown voltage compared with Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. A circuit design technique of using multiple parallel GaN FETs is presented. In this technique, the multiple parallel FETs have independently controllable gate voltages. Compared to a large single FET, using multiple FETs and biasing them individually helps to improve the linearity through the cancellation of nonlinear distortion components. Experimental results show the highest linearity improvement compared with the other state-of-the-art linearization schemes. The technique demonstrated is the first time implementation in GaN technology. The technique is a simple and cost-effective solution for improving the linearity of the amplifier circuits. Applications include base station amplifiers, mobile handsets, radars, satellite communication, etc.

As the oil industry continues to drill deeper to reach new wells, electronics are being required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, gain of 16.1 dB, and P1dB of 19.1 dBm from 230.5MHz — 285.5MHz. The maximum variation with temperature from 25°C to 230°C is 1.53dB for NF and 0.65dB for gain. / Master of Science

In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can adapt to multi-dimensional channel conditions, are proposed. Secondly, the thesis proves that adaptive systems can have multiple modes of operation depending upon the throughput requirements of the system. Two such modes were demonstrated: one optimizing the energy-per-bit (energy priority mode) and another achieving the lowest power consumption at the highest throughput (data priority mode). Finally, to achieve process tolerant channel adaptive operation a self-learning methodology is proposed which learns the optimal re-configuration setting for the system on-the-fly. Implications of the research are discussed and future avenues of further research are proposed.