Orientador: Luiz Carlos Kretly / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-11T03:07:44Z (GMT). No. of bitstreams: 1 Capovilla_CarlosEduardo_D.pdf: 7813094 bytes, checksum: 52ab9727d246649f4c3628a9a462e9c2 (MD5) Previous issue date: 2008 / Resumo: Esta pesquisa tem por objetivo a concepção de novas topologias de circuitos integrados e suas caracterizações para operação em sistemas de rádio-recepção. O projeto e a fabricação de chaves de RF, LNAs, mixer e VCOs são apresentados. A técnica SMILE (Spatial MultIplexing ofLocal Elements) foi adotada devido às suas vantagens e funcionalidade para a otimização física de antenas inteligentes. Essa técnica requer um chaveamento sequencial das antenas do arranjo e para tal foi desenvolvido um controle de chaveamento acionado por um VCO digital. A demultiplexação analógica do sinal é implementada através de um OTA e chaves analógicas diferenciais. Assim, além da introdução de novas topologias de circuitos integrados, este trabalho estabelece procedimentos de projeto e simulação associados à validação dos dispositivos fabricados. Palavras-chave: circuitos integrados, rádio-recepção, antenas inteligentes, SMILE / Abstract: This research aims the conception of new topologies of integrated circuits and its characterizations for operation in radio-receiver systems. The design and fabrication of RF switches, LNAs, mixer, and VCOs are presented. The SMILE - Spatial MultIplexing of Local Elements - technique was adopted due to its advantages and functionality for the intelligent antennas physical optimization. This technique requires a sequential switching of the antennas and for this purpose a switch driver with a digital VCO was developed. The analog demultiplexation of the signal is implemented with OTA and differential analog switches. Thus, besides the introduction of new integrated circuit topologies, this work establishes procedures of design and simulation together with the manufactured devices validation. Keywords: integrated circuits, radio-reception, smart antennas, SMILE / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Orientador: Luiz Carlos Kretly / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-11T01:55:52Z (GMT). No. of bitstreams: 1 Silva_AndreTavoradeAlbuquerque_D.pdf: 5543671 bytes, checksum: 26990143f84fbd9e80d60304ebc8febc (MD5) Previous issue date: 2008 / Resumo: Este trabalho apresenta dois tópicos de pesquisa, o primeiro é referente ao projeto e desenvolvimento da tecnologia de fabricação de Chaves MEMS (Micro Electro Mechanical System) de RF e o segundo é o projeto de circuitos integrados. No que se refere a chaves MEMS, descreve-se o processo e a metodologia para projeto de Chaves MEMS paralela sobre linha de transmissão coplanar (CPW). A estrutura é composta de uma ponte metálica suspensa em ambos os lados por dois postes metálicos conectados ao plano de terra. As chaves são projetadas para uma baixa tensão de ativação (16 V) e com larga banda de operação em freqüência (400 MHz ¿ 4GHz) possibilitando seu uso na maioria dos padrões de sistemas de comunicação. Também é descrita a metodologia do projeto auxiliado por simulações eletromecânicas e eletromagnéticas e finalmente é apresentada a caracterização de 4 chaves construídas. Após extensa pesquisa na literatura técnico-científica, foi identificado que este é o primeiro trabalho no Brasil dedicado ao desenvolvimento de tecnologia de fabricação de chaves MEMS. Os projetos de circuitos integrados foram realizados em tecnologia CMOS 0,35 µm e incluem: multiplicador de tensão e oscilador em anel, chaveador SPDT (Single Pole Double Through), amplificador de baixo ruído e modulador BPSK. Sendo os circuitos multiplicador de tensão e oscilador em anel projetados para aplicações em chaves MEMS. Os circuitos SPDT, amplificador de baixo ruído e modulador BPSK são parte integrante de Front-End de RF, com recepção em 1,8 GHz (banda D - GSM) e transmissão em 868,3 MHz (padrão Zigbee). São descritos os guias de projeto para cada circuito com simulações e desenho de layout. Especificamente para os circuitos, multiplicador de tensão e amplificador de baixo ruído são apresentadas novas topologias. Estes dois circuitos estão em via de preparação de patente. Finalmente, as caracterizações de cada circuito são apresentadas, com exceção do modulador BPSK / Abstract: This work presents two main research topics: the first refers to the design and the development of a fabrication technology for RF MEMS (Micro Electromechanical Systems) Switches and the second to the design of RF integrated circuits. In relation to MEMS switches, it describes the fabrication process and the design methodology of Shunt MEMS switches over a coplanar transmission line (CPW). The structure is composed by a metallic bridge anchored on both ends by two metallic posts connected to the ground plane. The switches are designed to operate at low activation voltage (16 V) and with a large band of operating frequency (400 MHz ¿ 4GHz), making possible its use in many communication systems. It is also described a design methodology assisted by electromechanical and electromagnetic simulations, and finally it is presented the characterization of 4 switches. After extensive search in technical literature, it was identified that this is the first work in Brazil dedicated to the technology development and fabrication of MEMS switches. The integrated circuits designs are realized in CMOS 0.35 µm technology and includes: charge pump and ring oscillator, SPDT switcher (Single Pole Double Through), low noise amplifier and BPSK modulator. The circuits charge pump and ring oscillator are intended to MEMS switches applications. The circuits SPDT, low noise amplifier and BPSK modulator are integrating parts of a RF Front-End, with reception at 1.8 GHz (band D ¿ GSM) and transmission at 868.3 MHz (ZigBee standard). The design guidelines to each circuit are described, with simulations and layout drawing. Specifically to the circuits charge pump and low noise amplifier, it is presented new topologies with innovation in the area. These two circuits have their patent process under preparation. Finally, the characterization of each circuit is presented, with exception of the BPSK modulator / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur Silicium. / The interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver.

Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateur. / Thesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator.

The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

No description available.

<p>Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnog<br />primopredajnika neposredno nakon antene. NJegova uloga je da ulazni<br />signal određene frekvencije i male snage izdvoji i pojača iznad nivoa<br />šuma prijemnika. U okviru doktorske disertacije prikazane su i<br />opisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOS<br />tehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Na<br />osnovu dobijenih rezultata, u 0,18 &mu;m UMC CMOS tehnologiji<br />realizovan je i fabrikovan NŠP jednostavne topologije, koja<br />predstavlja zbir dva pristupa, pojačavačkog stepena kaskodne<br />strukture sa povratnom spregom i stepena sa višestrukim<br />iskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od<br />3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, a<br />zatim je i izvršena njegova karakterizacija.</p> / <p>In the transceiver chain the low noise amplifier (LNA) is placed in the frontend<br />of the receiver after the antenna. The LNA needs to isolate and amplify<br />received weak signal at a specific frequency above the noise level of the<br />receiver. In the scope of this doctoral dissertation methods for designing<br />ultra-wideband (UWB) LNA in CMOS technology are presented and<br />described. Nine new LNA configurations were proposed. Based on the<br />obtained results, simple LNA configuration, obtained by merging casode<br />feedback topology and current-reuse technique, was realized and fabricated<br />in 0.18 &mu;m UMC CMOS technology. The LNA is designed for the frequency<br />band from 3.1 to 5 GHz. In addition, the method for measurement LNA<br />parameters is described and the proposed LNA was characterized.</p>

Although the majority of wireless receiver subsystems have moved to digital signal processing over the last decade, the low noise amplifier (LNA) remains a crucial analogue subsystem in any design being the dominant subsystem in determining the noise figure (NF) and dynamic range of the receiver as a whole. In this research a novel LNA configuration, namely the LC-ladder and capacitive shunt-shunt feedback topology, was proposed for use in the implementation of very wideband LNAs. This was done after a thorough theoretical investigation of LNA configurations available in the body of knowledge from which it became apparent that for the most part narrowband LNA configurations are applied to wideband applications with suboptimal results, and also that the wideband configurations that exist have certain shortcomings. A mathematical model was derived to describe the new configuration and consists of equations for the input impedance, input return loss, gain and NF, as well as an approximation of the worst case IIP3. Compact design equations were also derived from this model and a design strategy was given which allows for electronic design automation of a LNA using this configuration. A process for simultaneously optimizing the circuit for minimum NF and maximum gain was deduced from this model and different means of improving the linearity of the LNA were given. This proposed design process was used successfully throughout this research. The accuracy of the mathematical model has been verified using simulations. Two versions of the LNA were also fabricated and the measured results compared well with these simulations. The good correlation found between the calculated, simulated and measured results prove the accuracy of the model, and some comments on how the accuracy of the model could be improved even further are provided as well. The simulated results of a LNA designed for the 1 GHz to 18 GHz band in the IBM 8HP process show a gain of 21.4 dB and a minimum NF of only 1.7 dB, increasing to 3.3 dB at the upper corner frequency while maintaining an input return loss below -10 dB. After steps were taken to improve the linearity, the IIP3 of the LNA is -14.5 dBm with only a small degradation in NF now 2.15 dB at the minimum. The power consumption of the respective LNAs are 12.75 mW and 23.25 mW and each LNA occupies a chip area of only 0.43 mm2. Measured results of the LNA fabricated in the IBM 7WL process had a gain of 10 dB compared to an expected simulated gain of 20 dB, however significant path loss was introduced by the IC package and PCB parasitics. The S11 tracked the simulated response very well and remained below -10 dB over the feasible frequency range. Reliable noise figure measurements could not be obtained. The measured P1dB compression point is -22 dBm. A 60 GHz LNA was also designed using this topology in a SiGe process with ƒT of 200 GHz. A simulated NF of 5.2 dB was achieved for a gain of 14.2 dB and an input return loss below -15 dB using three amplifier stages. The IIP3 of the LNA is -8.4 dBm and the power consumption 25.5 mW. Although these are acceptable results in the mm-wave range it was however found that the wideband nature of this configuration is redundant in the unlicensed 60 GHz band and results are often inconsistent with the design theory due to second order effects. The wideband results however prove that the LC-ladder and capacitive shunt-shunt feedback topology is a viable means for especially implementing LNAs that require a very wide operating frequency range and also very low NF over that range. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

The integration of wireless communication, e.g., in real- or quasi-real-time applications, is related to many challenges such as energy consumption, communication range, quality of service, and reliability. The improvement of wireless sensor networks (WSN) performance starts by enhancing the capabilities of each sensor node. To minimize latencies without increasing energy consumption, wake-up receiver (WuRx) nodes have been introduced in recent works since they can be always-on or power-gated with short latencies by a power consumption in the range of some microwatts. Compared to standard receiver technologies, they are usually characterized by drawbacks in terms of sensitivity. To overcome the limitation of the sensitivity ofWuRxs, a design of a low noise amplifier (LNA) with several design specifications is required. The challenging task of the LNA design is to provide equitable trade-off performances such as gain, power consumption, the noise figure, stability, linearity, and impedance matching. The design of fast settling LNA for a duty-cycled WuRx front-end operating at a 868 MHz frequency band is investigated in this work. The paper details the trade-offs between design challenges and illustrates practical considerations for the simulation and implementation of a radio frequency (RF) circuit. The implemented LNA competes with many commercialized designs where it reaches single-stage 12 dB gain at a 1.8 V voltage supply and consumes only a 1.6 mA current. The obtained results could be made tunable by working with off-the-shelf components for different wake-up based application exigencies.

Silicon-on-Insulator (SOI) CMOS technology constitutes a good candidate for mixed signal RF CMOS applications. Due to its low junction capacitance and reduced leakage current, SOI provides reduced static and dynamic power consumption of the digital logic combined with increased cut-off frequencies. Moreover, in terms of passive device integration the major benefit of SOI when compared to the conventional bulk is the possibility to use a high resistivity substrate which allows a drastic reduction of substrate losses allowing a high quality factor of the passive devices. Another issue is the harsh environment applications. Electronics capable of operating at high temperatures are required in several industrial applications, including the automobile industry, the aerospace industry, the electrical and nuclear power industries, and the well-logging industry. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 300°C has been demonstrated. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latch up and reduced leakage current. In this context, various topologies of integrated transmission lines and spiral inductors implemented on standard and high substrate resistivities have been analyzed over a large temperature range. The temperature behavior of the SOI transistors is presented. The main figures-of-merit of the SOI MOSFETs are analyzed and the extraction of the extrinsic and intrinsic parameters of the small signal equivalent circuit is performed. Also, an example of RF circuit applications of the SOI technology, based on a fully integrated Low-Noise Amplifier for low-power and narrow-band applications, is investigated and characterized at high temperature. The main figures-of-merit of the designed circuit are extracted and discussed. The good results show that the SOI technology is now emerging as a good candidate for the realization of analog integrated circuits for low-power and high-temperature applications.