In this master degree work, a digital attenuator and a low noise amplifier (LNA) have been designed and integrated with the RF front-end receiver for IEEE 802.11b Wireless LAN standard. Firstly, the 4-bit digitally controlled attenuator has been designed with theattenuation range of 50 to 80 dB and reflection coefficient less than -25 dB. Next, the single stage wide band low noise amplifier with voltage gain larger than 14 dB and noise figure below 4 dB has been designed to operate at frequency 2.4 GHz. Finally, the integration with a down-conversion mixer has been done and evaluated its performance. The attenuator and low noise amplifier desired in this thesis have been implemented using standard CMOS 0.35µm technology and validated by the simulation tools Cadence Spectre-RF.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.

In this work, a highly linear broadband Low Noise Amplifier (LNA) is presented. The linearity issue in broadband Radio Frequency (RF) front-end is introduced, followed by an analysis of the specifications and requirements of a broadband LNA through consideration of broadband, multi-standard front-end design. Metal-Oxide- Semiconductor Field-Effect Transistor (MOSFET) non-linearity characteristics cause linearity problems in the RF front-end system. To solve this problem, feedback and the Derivative Superposition Method linearized MOSFET. In this work, novel linearization approaches such as the constant current biasing and the Derivative Superposition Method using a triode region transistor improve linearization stability against Process, Supply Voltage, and Temperature (PVT) variations and increase high power input capability. After analyzing and designing a resistive feedback LNA, novel linearization methods were applied. A highly linear broadband LNA is designed and simulated in 65nm CMOS technology. Simulation results including PVT variation and the Monte Carlo simulation are presented. We obtained -10dB S11, 9.77dB S21, and 4.63dB Noise Figure with IIP3 of 19.18dBm for the designed LNA.

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit¡¦s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit. The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35£gm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration and resistive-feedback, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. The total power dissipation of the low noise amplifier is about 24.3mW at power supply 1.5 volt and the chip size is 1.283*1.008mm2. The simulated result shows that S11 is under -8dB, S22 is under -10dB, the forward gain S21 is 12.6dB~15.3dB at 3.1-10.6GHz, the reverse isolation S12 is under -30dB, and the noise figure is 3.24dB~4.84dB.

<p>In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.</p><p>Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.</p><p>The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.</p>

Αντικείμενο αυτής της διπλωματικής εργασίας είναι ο σχεδιασμός ενός αναλογικού ενισχυτικού κυκλώματος χαμηλού θορύβου το οποίο θα λειτουργεί σε υψηλές συχνότητες. Ο ενισχυτής αυτός προορίζεται για χρήση στο analog front end κυκλωμάτων τα οποία θα υποστηρίζουν πρωτόκολλα μεταφοράς πληροφορίας σε δίκτυα ισχύος (Power Line Communication, Internet of Things). Για τον σχεδιασμό γίνεται η χρήση της κλασικής θεωρίας μικροηλεκτρονικών κυκλωμάτων αλλά και της μικροκυματικής θεωρίας. Παρουσιάζονται οι διάφορες τοπολογίες των τρανζίστορ BJT, γίνεται μία παρουσίαση των βασικότερων πηγών θορύβου και αναφέρονται βασικές αρχές των S παραμέτρων και της προσαρμογής εμπέδησης. Ο ενισχυτής κοινού εκπομπού απορρίφθηκε καθώς αποδείχθηκε αμφίπλευρος οπότε καταλήξαμε στην επιλογή της cascode τοπολογίας η οποία προσδίδει ευστάθεια, απομόνωση και καλή γραμμικότητα. Η απόλυτη προδιαγραφή που τέθηκε για το θόρυβο δεν επιτεύχθηκε και οπότε αναφέραμε τους λόγους που οδήγησαν σε αυτό και προτείναμε πιθανές λύσεις μέσω άλλων υλοποιήσεων. / The subject of this diploma thesis is the design of a low noise high-frequency analogue amplifier. The amplifier is designed to be used in the analog front end of circuits designed to support protocols that control the transmission of information over power lines (internet of things). To achieve this goal we make use of classic microelectronics theory but also microwave theory. The topologies of the BJT transistors are presented, we also go through the basic noise production reasons and we also make a short reference on the s-parameters and on the basic principles of impedance matching. The common emitter amplifier proved to be bilateral, so the cascode amplifier, which provides stability, isolation and linearity, was preferred. The noise specification was not achieved so we present the basic reasons of this, as well as we propose possible solutions.

Το αντικείμενο της παρούσης διπλωματικής επικεντρώνεται στη σχεδίαση ανάπτυξη και μέτρηση κυκλώματος κάτω μεταλλάκτη (down converter) συχνότητας στην περιοχή 1 έως 6 GHz. Η αρχιτεκτονική περιλαμβάνει ενισχυτή χαμηλού θορύβου (LNA) κατανεμημένης τοπολογίας (distributed amplifier), μίκτη καθώς και ενισχυτές και φίλτρα στην ενδιάμεση συχνότητα. Ο σχεδιασμός συνοδεύεται από μετρήσεις όπου και διαπιστώνεται η σύγκλιση με τα αποτελέσματα εντατικών εξομοιώσεων. Κύρια εργαλεία του σχεδιασμού απετέλεσαν κυκλωματικοί και ηλεκτρομαγνητικοί εξομοιωτές. / The object of this thesis focuses on design development and measurement down converter circuit in the frequency range 1 to 6 GHz. The architecture includes low noise amplifier (LNA) Distributed topology (distributed amplifier), mixer and amplifiers and filters in intermediate frequency. The design is accompanied by measurements and found where the convergence of the results of intensive simulations. Main tools of design were kyklomatikoi and electromagnetic simulators.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: This thesis presents the design, construction and measurement of two wide-band LNA’s for the SKA-Mid range (350-1200 MHz). The first wide-band LNA involves the investigation of classic low noise amplifier techniques, which includes basic noise theory, stability analysis, feedback design and the development of sophisticated matching techniques for ultra wide-band performance. Final measurements show a flat gain response equal to 19 dB, with a noise figure of 1.5 dB and an output return loss of 10 dB across the entire bandwidth. A multi-path cascading concept is introduced for the second low noise amplifier design, which aims to connect two single frequency amplifiers in parallel to operate from 500 to 700 MHz. The design process involves several optimization schemes to realise the matching networks for the cascaded topology and the noise performance of the device was confirmed by using multi-port noise theory. The prototype presents significant bandwidth improvements compared to a single frequency LNA design. Excellent agreement between the simulation and measurement were obtained with a flat gain response of 20 dB across a 2:1 bandwidth, with a low noise figure of 0.95 dB and an output return loss of 13 dB across the operation bandwidth of 400 to 800 MHz. / AFRIKAANSE OPSOMMING: Hierdie tesis behandel die ontwerp, konstruksie en meting van twee wyeband laeruis versterkers vir die SKA - Mid reeks (350–1200 MHz). Die eerste wyeband laeruis versterker, ondersoek klassieke laeruis versterker tegnieke wat insluit basiese ruisteorie, stabiliteit analise, terugvoerontwerp en die ontwikkeling van gevorderde aanpassingstegnieke vir ultra wyeband werkverrigting. Finale metings het ’n plat aanwins van 19 dB, met ’n ruisfiguur van 1.5 dB en ’n uittree-refleksie koëffisiënt van -10 dB oor die hele bandwydte vertoon. ’n Multi-pad konsep word bekend gestel vir die tweede laeruis versterker. Die ontwerp het twee enkel frekwensie laeruis versterkers in parallel verbind om vanaf 500 tot 700 MHz te werk. Die ontwerp proses bevat verskeie optimalisering skemas om die aanpassings netwerke vir die kaskade topologie te realiseer. Die ruissyfer van die versterker is bevestig deur die gebruik van multi-pad ruisteorie. Die prototipe het beduidende bandwydte verbeterings vertoon in vergelyking met ’n enkel frekwensie versterker ontwerp. ’n Uitstekende ooreenkoms tussen die simulasie en meting was verkry met ’n plat aanwins van 20 dB oor ’n 2:1 bandwydte, met ’n laeruisfiguur van 0.95 dB en ’n uittree-refleksie koëffisiënt van -13 dB oor die bandwydte van 400-800 MHz.

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).