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Low Dropout Linear Regulator & Dynamic Level Shifter Logic in a 0.09 m CMOS TechnologyChen, Sheng-quane 29 July 2009 (has links)
As the application of the consuming electronic products being used extensively, more and more functions can be worked on the same chip. Different function blocks may need different supply voltage. Considering of power consumption, circuit operated at low voltage and low current can achieve power reduction. Due to the energy crisis nowadays, plenty of products begin to focus on the green power. The main advantage of green power is saving power, which will not affect the efficiency. In addition, while the CMOS technology process evolves all the time, the stability of the operation voltage needs to be reduced by the advancement. Thus, the power management in a 3D graphic chip application is going to be introduced in this thesis. Utilizing the linear regulator to reduce the DC to 1.2, 1.1, 1.0, 0.9 and 0.8 V from 3.3V, and support a stable voltage for core circuits and I/O circuits. With the emphasis on the circuit efficiency is affected by power management, the level shifter to embed normal useful digital logic is also investigated. When using in the logic gates, it can reduce power consumption simultaneously. Therefore, it is important to adopt power IC in the future.
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Aging Analysis and Aging-Resistant Design for Low-Power CircuitsParthasarathy, Krupa January 2014 (has links)
No description available.
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Voltage scaling interfaces for multi-voltage digital systems / Interfaces de escalonamento de tensão para sistemas digitais de multiplas tensõesLlanos, Roger Vicente Caputo January 2015 (has links)
Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Voltage scaling interfaces for multi-voltage digital systems / Interfaces de escalonamento de tensão para sistemas digitais de multiplas tensõesLlanos, Roger Vicente Caputo January 2015 (has links)
Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Voltage scaling interfaces for multi-voltage digital systems / Interfaces de escalonamento de tensão para sistemas digitais de multiplas tensõesLlanos, Roger Vicente Caputo January 2015 (has links)
Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Theory of super power saving circuits and configurations for mixed signal CPU for smartcard application / Teori om extremt energisparande kretsar och konfigurationer för mixed signal CPU för smartcard applikationKleist, Anders January 2004 (has links)
<p>Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. </p><p>This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.</p>
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Theory of super power saving circuits and configurations for mixed signal CPU for smartcard application / Teori om extremt energisparande kretsar och konfigurationer för mixed signal CPU för smartcard applikationKleist, Anders January 2004 (has links)
Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.
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Integrierte Hochvolt-Ansteuerelektronik für Mikroaktoren mit elektrostatischem AntriebHeinz, Steffen 29 August 2006 (has links) (PDF)
Die vorliegende Arbeit behandelt integrierte Hochvolt-Schaltungen für die Ansteuerung elektrostatisch arbeitender Mikroaktoren und Mikroaktorarrays. Im Besonderen wird auf die Gesichtspunkte der Treiberschaltungen von Torsionsspiegelarrays eingegangen. Es werden verschiedene Verstärkerbetriebsarten und Schaltungsvarianten hinsichtlich der Ansteuerung kleiner kapazitiver Lasten beurteilt. Für die hocheffiziente Signalübertragung zwischen Low-Side und High-Side in geschalteten Hochvolt-Verstärkern wird ein neuer dynamischer Level-Shifter vorgestellt. Anhand eines gebondeten Mikroelektronik-Mikromechanik-Aufbaus für ein Hadamard-Transformations-Spektrometer werden die speziellen Aspekte des Elektronikentwurfs für ein System-in-Package aufgezeigt.
Als Entwurfsgrundlage wird ein Überblick über die wesentlichen Isolationstechnologien für integrierte Hochvolt-Schaltungen und über die Bauelementemodellierung in einer SOI-Technologie ausgearbeitet. Außerdem werden die Vor- und Nachteile der wichtigsten Antriebsprinzipien von Mikroaktoren zusammengefasst.
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Vysokonapěťové struktury pro galvanickou iziolaci v integrovaných obvodech / High-Voltage Structures for Galvanic Isolation in Integrated CircuitsPtáček, Karel January 2020 (has links)
Tato dizertační práce představuje novou techniku laterární rezonanční vazby, která je využita v návrhu galvanicky izolovaného posouvače úrovně, který je následně implementován v 800 V půlmůstkovém kontroléru pro průmyslové aplikace. Ve srovnání s tradičními galvanickými izolátory jsou výrobní náklady tohoto řešení nižší. Pro aplikace vyžadující vyšší úroveň galvanické izolace je popsán následný vývoj galvanicky izolovaného posouvače úrovně, který využívá pouze jeden galvanicky oddělený posouvač úrovní pro komunikaci v obou směrech, což výrazně snižuje plochu struktury izolátoru. Jako součást následného návrhu je představen galvanický izolátor který je schopen přenášet analogovou hodnotu napětí. Analogový izolátor byl testován v reálné aplikaci síťového spínaného zdroje jako náhrada standardního optočlenu. Tato konstrukce umožňuje integraci primárních a sekundárních obvodů v jednom pouzdře, což umožní snížit složitost a cenu spínaného zdroje.
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Integrierte Hochvolt-Ansteuerelektronik für Mikroaktoren mit elektrostatischem AntriebHeinz, Steffen 24 August 2006 (has links)
Die vorliegende Arbeit behandelt integrierte Hochvolt-Schaltungen für die Ansteuerung elektrostatisch arbeitender Mikroaktoren und Mikroaktorarrays. Im Besonderen wird auf die Gesichtspunkte der Treiberschaltungen von Torsionsspiegelarrays eingegangen. Es werden verschiedene Verstärkerbetriebsarten und Schaltungsvarianten hinsichtlich der Ansteuerung kleiner kapazitiver Lasten beurteilt. Für die hocheffiziente Signalübertragung zwischen Low-Side und High-Side in geschalteten Hochvolt-Verstärkern wird ein neuer dynamischer Level-Shifter vorgestellt. Anhand eines gebondeten Mikroelektronik-Mikromechanik-Aufbaus für ein Hadamard-Transformations-Spektrometer werden die speziellen Aspekte des Elektronikentwurfs für ein System-in-Package aufgezeigt.
Als Entwurfsgrundlage wird ein Überblick über die wesentlichen Isolationstechnologien für integrierte Hochvolt-Schaltungen und über die Bauelementemodellierung in einer SOI-Technologie ausgearbeitet. Außerdem werden die Vor- und Nachteile der wichtigsten Antriebsprinzipien von Mikroaktoren zusammengefasst.
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