In this thesis, three different types of low-noise amplifiers (LNA’s) have been designed using a 0.25 mm SiGe BiCMOS process. Firstly, a single-stage amplifier has been designed with 11 dB gain and 3.7 dB noise figure at 8 GHz. Secondly, a cascode two-stage LNA with 16 dB gain and 3.8 dB noise figure at 8 GHz is also described. Finally, a cascade two-stage LNA with a wide-band RF performance (a gain larger than unity between 2-17 GHz and a noise figure below 5 dB between 1.7 GHz and 12 GHz) is presented. These SiGe BiCMOS LNA’s could for example be used in the microwave receivers modules of advanced phased array antennas, potentially making those more cost- effective and also more compact in size in the future. All LNA designs presented in this report have been implemented with circuit layouts and validated through simulations using Cadence RF Spectre.

This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the feedback capacitor in parallel with the resistor to achieve matching with the control input voltage, in addition to adjusting the feedback resistor can control the noise. The LNA dissipates 13.2 mW power and achieves input return loss (S11) below -10dB, output return loss (S22) below -10 dB, forward gain (S21) of 11.3~14.5dB, reverse isolation (S12) below -40dB, and noise figure (NF) of 3~3.18 dB. 1-dB compression point (P1dB) of -24 dBm and input third-order inter-modulation point (IIP3) of -14 dBm .

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content.

In this work, a highly linear broadband Low Noise Amplifier (LNA) is presented. The linearity issue in broadband Radio Frequency (RF) front-end is introduced, followed by an analysis of the specifications and requirements of a broadband LNA through consideration of broadband, multi-standard front-end design. Metal-Oxide- Semiconductor Field-Effect Transistor (MOSFET) non-linearity characteristics cause linearity problems in the RF front-end system. To solve this problem, feedback and the Derivative Superposition Method linearized MOSFET. In this work, novel linearization approaches such as the constant current biasing and the Derivative Superposition Method using a triode region transistor improve linearization stability against Process, Supply Voltage, and Temperature (PVT) variations and increase high power input capability. After analyzing and designing a resistive feedback LNA, novel linearization methods were applied. A highly linear broadband LNA is designed and simulated in 65nm CMOS technology. Simulation results including PVT variation and the Monte Carlo simulation are presented. We obtained -10dB S11, 9.77dB S21, and 4.63dB Noise Figure with IIP3 of 19.18dBm for the designed LNA.

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications.

The objective of this thesis is to design RF circuits using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for communication system. The packaging effect for the SiGe chip using liquid crystal polymer (LCP) is presented and methodology to derive the model for the package is discussed. Chapter 1, we discuss the overview and benefits of SiGe HBT technology in high frequency circuit design. Chapter 2 presents the methodology of the low noise amplifier (LNA) design and discusses the trade-off between the noise and gain matching. The technique for achieving simultaneous noise and gain matching for the LNA is also presented. Chapter 3 presents an L-band cascaded feedback SiGe low noise amplifier (LNA) design for use in Global Position System (GPS) receivers. Implemented in a 200 GHz SiGe BiCMOS technology, the LNA occupies 1 x 1 millimeter square (including the bondpads). The SiGe LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1-dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of -3.98 dBm. Lastly, Chapter 4 covers the packaging techniques for the SiGe monolithic integrated circuit (MMIC). We present the modeling of a liquid crystal polymer (LCP) package for use with an X-band SiGe HBT Low Noise Amplifier (LNA). The package consists of a 2 mil LCP laminated over an embedded SiGe LNA, with vias in the LCP serving as interconnects to the LNA bondpads. An accurate model for the packaging interconnects has been developed and verified by comparing to measurement results, and can be used in chip/package co-design.

With the advancement in wireless communication, there has been a lot of overlap in the frequency spectrum used by different applications in the lower frequency band. Also there is an ever-increasing demand for high-speed wireless data transfer. Due to the aforementioned reasons, a lot of work is being done recently in the unlicensed 60GHz bandwidth due to the high data rates it can support. But it is tough to achieve long-range point-to-point transmission at this frequency due to the limited output power and high path losses. A phased array system is a viable solution at these mmWave frequencies to achieve highly directive long-range point-to-point communication. The objective of this research is the design and implementation of phase shifters, VCO and LNA for mmWave phased array system. In this work, active and passive quadrature generation schemes integrated with a vector modulator have been proposed that can be used to produce arbitrary phase shift with a deterministic resolution at the LO signal. Also, alternate IF and PLL based phase shifting schemes for a mmWave phased array system have been proposed. A complete design procedure from parasitic modeling of devices to verification of the design using EM simulations has been discussed in this work. The simulation results are compared with actual measurement results from the fabricated chip and the performance of the various circuits has been analyzed. Furthermore, the designs of VCO and low noise amplifier to be used in the mmWave phased array system are discussed here.

<p>In this thesis, three different types of low-noise amplifiers (LNA’s) have been designed using a 0.25 mm SiGe BiCMOS process. Firstly, a single-stage amplifier has been designed with 11 dB gain and 3.7 dB noise figure at 8 GHz. Secondly, a cascode two-stage LNA with 16 dB gain and 3.8 dB noise figure at 8 GHz is also described. Finally, a cascade two-stage LNA with a wide-band RF performance (a gain larger than unity between 2-17 GHz and a noise figure below 5 dB between 1.7 GHz and 12 GHz) is presented. </p><p>These SiGe BiCMOS LNA’s could for example be used in the microwave receivers modules of advanced phased array antennas, potentially making those more cost- effective and also more compact in size in the future. </p><p>All LNA designs presented in this report have been implemented with circuit layouts and validated through simulations using Cadence RF Spectre.</p>

Ultra-wide band (UWB) 6-9 GHz antenna, band pass filter and low-noise amplifier (LNA) optimization using co-simulation of the RF front-end. At higher frequencies, carefully conducted design methodologies are required for RF front-end parameter optimization, such as power gain and low noise figure with low power consumption.

La dernière décennie à vu l'explosion des technologies de communication sans fils. Les normes se sont multipliées de sorte que les fonctionnalités GSM, GPS, WIFI, Bluetooth et autres cohabitent parfois au sein du même terminal. Les réseaux de capteurs (Wireless area network WSN) incluant les réseaux de capteur WPAN (Wireless Personnel Area Network) seront amenés à jouer un rôle important dans l'environnement de demain au même titre que les normes sans fils grand public que nous venons de mentionner. Le déploiement de ces capteurs à grande échelle a été rendu possible par la réduction du coût de leur fabrication via la miniaturisation des procédés de fabrication propres à la technologie CMOS. Cependant, la consommation énergétique de ces circuits doit être très réduite permettant ainsi de fonctionner dans le cas où ces mêmes capteurs sont associés à une batterie compacte embarquée de durée de vie réduite. A défaut il serait nécessaire de pouvoir se contenter de l'énergie récupérable - en quantité limité - disponible dans l'environnement direct de ces capteurs. Cette contrainte de consommation électrique réduite ainsi que la nécessité de profiter au maximum de la miniaturisation du procédé CMOS amène à considérer la conception de circuits radio sous l'angle du faible encombrement surfacique et de la consommation statique la plus faible possible. Ces contraintes sont parfois contradictoires avec les architectures classiques connues de ces circuits radio constituants les capteurs déployés.es travaux présentés dans le cadre de cette thèse s'attachent à proposer des solutions afin de répondre à ces critères de consommation et de coût. Nous nous sommes intéressés au cas des amplificateurs faible bruit (Low Noise Amplifier - LNA) et à la possibilité de réaliser ce composant critique pour le lien RF sans utiliser d'inductance intégrées tout en limitant au maximum la consommation électrique. Plusieurs solutions innovantes ont été étudiées afin de répondre à cet objectif. Ces travaux nous ont conduit à la réalisation de plusieurs prototypes de circuits en technologie CMOS 65nm et 130nm qui permettent de comprendre les limites et les avantages d'une telle approche. La première partie présentera une première approche consistant à émuler une inductance à l'aide de composants actifs et ainsi à résoudre le problème de l'encombrement propre au inductance passives. Nous verrons en quoi cette approche peut présenter des limites pratiques pour une application radio. La seconde partie présentera la réalisation d'un LNA très basse consommation et large bande qui n'utilise pas d'inductance et présentant des performances améliorées vis à vis des topologies connues de LNA à faible consommation. Nous conclurons ensuite par les perspectives ouvertes suite à ces travaux et les autres approches possibles pour répondre aux contraintes de la basse consommation et du faible coût.