In this dissertation, an all-fiber-based single frequency nanosecond pulsed laser system at ~ 1918.4 nm in master-oscillator-power-amplifier (MOPA) configuration is present. The nanosecond pulse seed is achieved by directly modulating a continuous wave (CW) single frequency fiber laser using a fast electro-optical modulator (EOM) driven by an arbitrary waveform generator (AWG). One piece of single mode, large core, polarization-maintaining (PM) highly thulium-doped (Tm-doped) germanate glass fiber (LC-TGF) is used to boost the pulse power and pulse energy of these modulated pulses in the final power amplifier. This laser system can work in both high power and high energy regime: in high power regime, to the best of our knowledge, the highest average power 16 W and peak power 78.1 kW are achieved for single frequency transform-limited ~2.0 ns pulses at 500 kHz and 100 kHz repetition rate, respectively: In high energy regime, nearly 1 mJ and half mJ pulse energy is obtained for ~15 ns pulses at 1 kHz repetition rate and 5 kHz repetition rate, respectively. Theoretical modeling of the large-core highly Tm-doped germanate glass double-cladding fiber amplifier (LC-TG-DC-FA) is also present for 2&mum nanosecond pulse amplification. A good agreement between the theoretical and experimental results is achieved. The model can simulate the evolution of pump power, signal energy, pulse shape and the amplified stimulated emission (ASE) in the amplifier. It can also be utilized to investigate the dependence of the stored energy in the LC-TGF on the pump power, seed energy and repetition rate, which can be used to design and optimize the LC-TG-DC-FA to achieve higher pulse energy and average power. Two channel of high energy nanosecond pulses (at 1918.4 nm and 1938 nm) are utilized to generate THz wave in a quasi-phase-matched (QPM) gallium arsenide (GaAs) based on difference frequency generation. THz wave with ~ 5.4μW average power and ~18 mW peak power has been achieved. Besides, one model is built to simulate a singly resonated THz parametric oscillator. The threshold, the dependence of output THz energy on pump energy has been investigated through this model. One pump enhanced THz parametric oscillator has been proposed. The enhancement factor of the nanosecond pulses in a bow-tie ring cavity has been calculated for different pulse duration, cavity length and the transmission of the coupler. And the laser resonances in the ring cavity have been observed by using a piezo to periodically adjust the cavity length. We also build an all-fiber thulium-doped wavelength tunable mode-locked laser operating near 2&mum. Reliable self-starting mode locking over a large tuning range (>50 nm) using fiber taper based carbon nanotube (FTCNT) saturable absorber (SA) is observed. Spectral tuning is achieved by stretching another fiber taper. To the best of our knowledge, this is the first demonstration of an all-fiber wavelength tunable mode-locked laser near 2&mum.

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>??</i> m CMOS process technology.

The concern of this dissertation is the understanding and improvement of a class of lasers that is responsible for some of the shortest optical pulses available today. In particular, we seek ways to produce from synchronously pumped mode-locked dye laser systems, shorter pulses of higher intensity with improved pulse-to-pulse consistency. Specific topics.that are discussed herein include the study of the role of the pump pulse in synchronously pumped mode-locked lasers, the study of the pulse shaping and shortening due to an intracavity saturable absorber, and the study of a fundamental pulse train instability associated with these lasers.

A dual-wavelength mode-locked semiconductor vertical-external-cavity-surface-emitting laser is demonstrated. A semiconductor saturable absorber mirror allows for simultaneous mode locking of pulses centered at two center wavelengths with variable frequency spacing. The difference-frequency control is achieved with an intracavity etalon. Changing the finesse of the etalon enables the adjustment of the pulse duration between 6 and 35 ps. The emitted two-color pulses are modulated by a beat frequency in the terahertz range. Self-starting mode-locking with 0.8-W average output power is demonstrated.

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator's frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA.

As redes de distribuição de sinais de tempo - ou redes de sincronismo - têm a tarefa de distribuir os sinais de fase e freqüência ao longo de relógios geograficamente dispersos. Este tipo de rede é parte integrante de inúmeras aplicações e sistemas em Engenharia, tais como sistemas de comunicação e transmissão de dados, navegação e rastreamento, sistemas de monitoração e controle de processos, etc. Devido ao baixo custo e facilidade de implementação, a topologia mestre-escravo tem sido predominante na implementação das redes. Recentemente, devido ao surgimento das redes sem fio - wireless - de conexões dinâmicas, e ao aumento da freqüência de operação dos circuitos integrados, topologias complexas, tais como as redes mutuamente conectadas e small world têm ganhado importância. Essencialmente cada nó da rede é composto por um PLL - Phase-Locked Loop - cuja função é sincronizar um oscilador local a um sinal de entrada. Devido ao seu comportamentamento não-linear, o PLL apresenta um jitter com o dobro da freqüência de livre curso dos osciladores, prejudicando o desempenho das redes. Dessa forma, este trabalho tem como objetivo o estudo analítico e por simulação das condições que garantam a existência de estados síncronos, e do comportamento do jitter de fase nas redes de sincronismo. São analisadas as topologias mestre-escravo e mutuamente conectada para o PLL analógico clássico. / Network synchronization deals with the problem of distributing time and fre- quency among spatially remote locations. This kind of network is a constituent element of countless aplications and systems in Engineering, such as communication and data transmission systems, navigation and position determination, monitoring and process control systems, etc. Due to its low cost and simplicity, the master-slave architec- ture has been widely used. In the last few years, with the growth of the dynamically connected wireless networks and the rising operational frequencies of the integrated cir- cuits, the study of the mutually connected and small world architectures are becoming relevant. Essentially, each node of a synchronization network is constituted by a PLL - Phase-Locked Loop - circuit that must automatically adjust the phase of a local oscillator to the phase of an incoming signal. Because of its nonlinear behavior the PLL presents a phase jitter with the double of the free running frequency of the oscillators, impairing the network performance. Thus, this work aims to study, both analytically and by simulation, the existence conditions of the synchronous states and the behavior of the double frequency jitter in the synchronization networks. Specifically the One Way Master Slave (OWMS) and Mutually Connected (MC) network architectures for classical analogical PLLs are analyzed.

O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

Este trabalho apresenta o projeto de uma portadora que opera na frequência de 8.300 MHz para ser utilizado em moduladores vetoriais diretos com aplicação em sistemas embarcados de satélites. Foram realizados estudos sistêmicos de arquiteturas que operam nesta faixa de frequência com as características necessárias para atender as especificações da European Cooperation for Space Standardization, ECSS - Space Engineering Radio Frequency and Modulation da agência espacial europeia -ESA, que regulamenta as frequências e características para sistemas de transmissão para enlace de descida. A partir dos conhecimentos adquiridos nos estudos, é apresentada uma metodologia de projeto visando o atendimento das especificações definidas pela ECSS e a escolha de uma topologia de projeto. Foram realizadas simulações a nível sistêmico, utilizando o software Advanced Design System-ADS da fabricante Keysight Technologies, para definir as especificações de projeto dos circuitos que compõem o sistema de geração da portadora na banda X. O circuito da malha de sincronismo de fase - PLL opera na frequência de 2.075 MHz, onde seu sinal é amplificado e filtrado pela cadeia de amplificação na banda S cuja função é aumentar a isolação para minimizar os efeitos de pulling do oscilador controlado por tensão - VCO, devido à alta velocidade nas transições de tempo de subida e de descida dos sinais digitais I e Q. O filtro também é responsável por aumentar a rejeição de espúrios e harmônicos gerados pelos efeitos não lineares dos amplificadores. O sinal é enviado ao circuito multiplicador de frequências que gera o sinal na banda X e é filtrado por um filtro passa-faixas de linhas acopladas, rejeitando os sinais espúrios provenientes da saída do multiplicador de frequência. Na saída, o sinal passa por uma cadeia de amplificação na banda X para adequar o nível de potência à entrada dos moduladores vetoriais. Os circuitos projetados foram desenvolvidos utilizando tecnologia de microfita de linha. Os protótipos foram caracterizados, apresentando boa concordância com os resultados simulados, comprovando experimentalmente a metodologia de projeto utilizada neste trabalho assim como o atendimento das especificações sugeridas pela ECSS. / This work presents the project of an carrier that works in the frequency of 8,300 MHz to be used in direct vector modulator for embedded system application in satellites. It were realized system level studies of PLL topologies that work in this frequency range with the necessary features to provide the requirements from European Cooperation for Space Standardization, ECSS - Space Engineering Radio Frequency and Modulation of the European Space Agency - ESA, which is responsible for the frequencies and features regulation for downlink transmission system. With the knowledge acquired from the studies, it is presented a project method intending to the meet the requirements defined by the ECSS and the definition of a topology to the project. It were performed system level simulation, using the Advanced Design System - ADS tool, from Keysight Technologies, in order to define the design specifications in the project of the circuits of the X band carrier generator developed. The PLL circuit works in the frequency of 2,075 MHz, in which its signal is amplified and filtered for amplifier chain in S band, increasing the isolation to reduce the pulling effects in the voltage controlled oscillator, due to the high-speed transitions in the rise time and fall time of the digital signal I and Q. The filter is also responsible for increasing the rejection of spurious and harmonics generated by non-linear amplifiers effects. The signal is conducted to the frequency multiplier circuit that generates the X band signal and it is filtered by a coupled line bandpass filter, rejecting the spurious from the frequency multiplier output. At the output stage, the signal passes through a X band amplification chain in order to adequate the power level of the vector modulators input level. The specified circuits were designed and developed using microstrip line technology. The prototypes were characterized, presenting adequate results according to the data obtained by the simulations, experimentally reinforcing the project method used in this work as well as the meeting of the requirements suggested by the ECSS.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]

Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Electrical and Computer Engineering.