Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (p. 121-130).

Initial research in the field of organic electronics focused primarily on the improvements in material performance. Significant progress has been achieved in the case of organic field effect transistors, where reported mobility values are now over 5 orders of magnitude higher than those of early devices. As a consequence, the use of organic transistors is now being considered for real-world applications in the form of integrated logic circuits. This in turn presents many new challenges, as the logic circuit requirements are more demanding on the transistor characteristics and corresponding fabrication processes. This thesis investigates the feasibility of organic technology for its potential use in future low-cost, high-volume electronic applications. The research objectives were accomplished by practical evaluation of an organic logic circuit fabrication process. First, recent advances in the fabrication of organic circuits in terms of transistor structure, material usage and fabrication techniques are reviewed. Next, a lithographic logic circuit fabrication process using PVP gate dielectric and TIPS-pentacene organic semiconductor adapted from state of the art fabrication process is presented. The logic circuit design decisions and the methodology for the fabrication process are thoroughly documented. Using this process, zero-Vgs and diode-load inverter circuits were successfully fabricated. However, the process is in need of further refinement for more complex circuit designs, as the fabrication of a comparator circuit consisting of 11 transistors was unsuccessful. Two optimisation techniques that are compatible with the logic circuit fabrication process were also explored in this work. To improve the capacitive coupling of the dielectric layer, the use of a polymer nanocomposite dielectric was investigated. The nanocomposite is prepared by blending PVP solution with a high-k inorganic nanoparticle filler, barium strontium titanate. Using the nanocomposite dielectric, both single transistors and integrated logic circuits were successfully fabricated. This is the first report on the use of PVP and barium strontium titanate nanocomposite dielectric with a lithographic based logic circuit fabrication process. The use of PFBT modified Au contacts for the fabrication process was investigated to improve theperformance of the contact electrode layer. Using PFBT, mobility increased by one order of magnitude over untreated Au electrodes for the PVP and TIPS-pentacene transistors.

The object of my thesis is the realization of grammatical evolution in the Java programming language for solving problems of approximation of functions and synthesis of logical circuits. The application is practical used for testing and gathering data in context of using different purpose function and parallel grammatical evolution. The data are analyzed and evaluated.

Power dissipation in modern technologies is an important matter and overheating is a severe concern for both manufacturer (impossibility of introducing new and smaller scale technologies and limited temperature range for operating the product) and customer (power supply, which is especially important for mobile systems). One of the main profits that reversible circuit carries is theoretically the zero power dissipation in the sense that it is independent of underlying technology; irreversibility means heat generation. In the other words, reversible circuits may offer a feasible solution in the future that will aid certain reduction of the power loss. Reversible circuits are circuits that do not lose information during computation. These circuits can create unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between the input and the output vectors. Historically, the reversible circuits have been inspired by theoretical research in low power electronics as well as practical progress of bit-manipulation transforms in cryptography and computer graphics. Interest in reversible circuit is also sparked by its applications in several up-to-date technologies, such as Nanotechnology, Quantum Computing, Optical Computing, Quantum Dot Cellular Automata, and Low Power Adiabatic CMOS. However, the most important application of reversible circuits is in Quantum Computing. Logic synthesis methodologies for reversible circuits are very different from those for classical CMOS and other technologies. The dissertation introduces a new concept of reversible logic circuits synthesis based on EXOR-sum of Products-of-EXOR-sums (EPOE). The motivation for this work is to reduce the number of the multiple-controlled Toffoli gates as well as the numbers of their inputs. To achieve these reductions the research generalizes from the existing 2-level AND-EXOR structures (ESOP) commonly used in reversible logic to a mixture of 3-level EXOR-AND-EXOR structures and ESOPs. The approaches can be applied to reversible and permutative quantum circuits to synthesize both completely and incompletely specified single-output functions as well as multiple-output functions. This dissertation describes the research intended to examine the methods to synthesize reversible circuits based on this new concept. The examinations indicate that the synthesis of reversible logic circuits based on EPOE approach produces circuits with significantly lower quantum costs than the common ESOP approach.

Most part of my thesis is devoted to efficient automated logic synthesis of oracle processors. These Oracle Processors are of interest to several modern technologies, including Scheduling and Allocation, Image Processing and Robot Vision, Computer Aided Design, Games and Puzzles, and Cellular Automata, but so far the most important practical application is to build logic circuits to solve various practical Constraint Satisfaction Problems in Intelligent Robotics. For instance, robot path planning can be reduced to Satisfiability. In short, an oracle is a circuit that has some proposition of solution on the inputs and answers yes/no to this proposition. In other language, it is a predicate or a concept-checking machine. Oracles have many applications in AI and theoretical computer science but so far they were not used much in hardware architectures. Systematic logic synthesis methodologies for oracle circuits were so far not a subject of a special research. It is not known how big advantages these processors will bring when compared to parallel processing with CUDA/GPU processors, or standard PC processing. My interest in this thesis is only in architectural and logic synthesis aspects and not in physical (technological) design aspects of these circuits. In future, these circuits will be realized using reversible, nano and some new technologies, but the interest in this thesis is not in the future realization technologies. We want just to answer the following question: Is there any speed advantage of the new oracle-based architectures, when compared with standard serial or parallel processors?

No description available.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Timing hazards are common problems found in logic circuits. A new integrated hazard detection system (HDS), which is implemented in VHDL, is proposed to detect the static, the dynamic, and the function hazards in any logic circuit that is described structurally in VHDL. This system adopts the IEEE VHDL Model Standard Group 1076-1164 Nine-Valued Multiple-Valued Logic package. Without any designer-supplied arbitrary input test patterns, the system predicts which input combinations will cause hazards, reports what type of hazards, and provides detailed timing information on the hazards in the combinational logic circuit with fixed gate delays. / Master of Science

Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of logic mapping. Along with these benefits, regular structures in QCA's would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.

In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP circuits makes just-in-time power gating possible on a stage-by-stage basis. A new latch called Lazy Latch is introduced in this thesis. The lazy latch preserves its output and permits power gating of its larger transistors. The lazy latch is power efficient because it drives strongly only when necessary. A new latch called Blended Latch is proposed in this thesis which blends the advantages of the Conventional latches and the Lazy latches. Performance of power gating is evaluated by comparing the power-gated pipeline against the non-power gated pipeline. Power savings achieved are dependent on the duty cycle of operation. The fact that just-in-time power gating achieves power savings after it is idle for a minimum of 106 cycles makes it useful in limited applications where a quick start is required after long idle times.