Global ETD Search

71	A MOS switch-level simulator with delay calculation / Khordoc, Karim. January 1986 (has links) No description available. Simulation methods Electronic circuits Logic circuits
72	Hardware mapping of critical paths of a GaAs core processor for solid modelling accelerator / by Song Cui. Cui, Song January 1996 (has links) Bibliography: leaves 200-207. / xi, 207 leaves : ill. ; 20 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / The aim of this thesis is to design and implement the hardware mapping of critical paths of a GaAs Core Processor for a Solid Modelling Accelerator. The solid modelling accelerator is designed using GaAs/CMOS/B:CMOS unified technology. High speed GaAs technology is used in the core processor to deal with floating point intensive calculations, while CMOS technology is used where high speed outputs are not required. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996 Microprocessors Design and construction. Gallium arsenide semiconductors. Geometry, Solid. Logic circuits. CAD/CAM systems.
73	Viterbi decoders for mobile and satellite communications / Abdul Shakoor, Abdul Rafeeq, January 1900 (has links) Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 75-79). Also available in electronic format on the Internet.
74	Current mode logic latch and prescaler design optimization in 0.18um CMOS technology / Usama, Muhammad, January 1900 (has links) Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references. Also available in electronic format on the Internet.
75	Adaptable MOS current mode logic for multi-band frequency synthesizers / Houlgate, Mark January 1900 (has links) Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 143-146). Also available in electronic format on the Internet.
76	A 5.8mW fully integrated multi-gigahertz frequency synthesizer in 0.13-um CMOS / Karam, Vincent, January 1900 (has links) Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 54). Also available in electronic format on the Internet.
77	Probabilistic boolean logic, arithmetic and architectures Chakrapani, Lakshmi Narasimhan. January 2008 (has links) Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.
78	Automated mapping of clocked logic to quasi-delay insensitive circuits Shivakumaraiah, Lokesh, January 2007 (has links) Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.
79	Current and delay estimation in deep sub-micrometer CMOS logic circuits / Al-Mosawy, Muaayad. January 1900 (has links) Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 103-107). Also available in electronic format on the Internet.
80	Circuit design rules for mixed static and dynamics CMOS logic circuits. Ramirez Ortiz, Rolando, Carleton University. Dissertation. Engineering, Electronics. January 1999 (has links) Thesis (Ph. D.)--Carleton University, 1999. / Also available in electronic format on the Internet.

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