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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
71

Evaluation of SCIRTSS performance on sequential circuits biased against random sequences

Van Helsland, Marshall Camiel, 1943- January 1974 (has links)
No description available.
72

Synthesis and testing of reversible Toffoli circuits

Nayeem, Noor Muhammed January 2012 (has links)
Recently, researchers have been interested in reversible computing because of its ability to dissipate nearly zero heat and because of its applications in quantum computing and low power VLSI design. Synthesis and testing are two important areas of reversible logic. The thesis first presents an approach for the synthesis of reversible circuits from the exclusive- OR sum-of-products (ESOP) representation of functions, which makes better use of shared functionality among multiple outputs, resulting in up to 75% minimization of quantum cost compared to the previous approach. This thesis also investigates the previous work on constructing the online testable circuits and points out some design issues. A simple approach for online fault detection is proposed for a particular type of ESOP-based reversible circuit, which is also extended for any type of Toffoli circuits. The proposed online testable designs not only address the problems of the previous designs but also achieve significant improvements of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively. / xii, 82 leaves : ill. ; 29 cm
73

A MOS switch-level simulator with delay calculation /

Khordoc, Karim. January 1986 (has links)
No description available.
74

Hardware mapping of critical paths of a GaAs core processor for solid modelling accelerator / by Song Cui.

Cui, Song January 1996 (has links)
Bibliography: leaves 200-207. / xi, 207 leaves : ill. ; 20 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / The aim of this thesis is to design and implement the hardware mapping of critical paths of a GaAs Core Processor for a Solid Modelling Accelerator. The solid modelling accelerator is designed using GaAs/CMOS/B:CMOS unified technology. High speed GaAs technology is used in the core processor to deal with floating point intensive calculations, while CMOS technology is used where high speed outputs are not required. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996
75

Viterbi decoders for mobile and satellite communications /

Abdul Shakoor, Abdul Rafeeq, January 1900 (has links)
Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 75-79). Also available in electronic format on the Internet.
76

Current mode logic latch and prescaler design optimization in 0.18um CMOS technology /

Usama, Muhammad, January 1900 (has links)
Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references. Also available in electronic format on the Internet.
77

Adaptable MOS current mode logic for multi-band frequency synthesizers /

Houlgate, Mark January 1900 (has links)
Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 143-146). Also available in electronic format on the Internet.
78

A 5.8mW fully integrated multi-gigahertz frequency synthesizer in 0.13-um CMOS /

Karam, Vincent, January 1900 (has links)
Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 54). Also available in electronic format on the Internet.
79

Probabilistic boolean logic, arithmetic and architectures

Chakrapani, Lakshmi Narasimhan. January 2008 (has links)
Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.
80

Automated mapping of clocked logic to quasi-delay insensitive circuits

Shivakumaraiah, Lokesh, January 2007 (has links)
Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

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