Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Mary Ann Ingram, Committee Member; Lim, Sung Kyu, Committee Member; Riley, George F., Committee Member; Mooney III, Vincent J., Committee Chair; Pande Santosh, Committee Member. Includes bibliography.

No description available.

No description available.

The combinational logic circuits, which are performing some kind of logic function, can have several realizations. Realizations differ from each other, because of the elements of the database used in circuit. The test of one scheme realization do not necessarily fully verify mistakes of the other realization. The number of pathways in different realizations may also differ. The determination of dependence between test's propriety and the number of pathways for different circuits is the main task in this paper. After finding pathways in different realizations of circuit, and comparing these pathways, the number of fictional pathways in every realization is detected. Special software was developed for calculating pathways in VHDL combinational logic circuits. The software was used for testing pathway calculation operations of circuit realization and for comparing pathways of realizations. The main purpose of this paper was to develop software for pathways in VHDL circuit calculation, to perform experiments using this software, and to estimate the dependence for the number of pathways. The practise of developed software is wide. This system may be implemented for optimising the algorithm of test generator. Usually the test generation program generates more than minimum of possible tests. If the number of pathways in circuit is known, the developed software will help to optimise the algorithm of test generation so that the minimum number of tests would be generated.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.

Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [90]-94).

Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references (p.68-73).

Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (leaves 147-153).

No description available.

The performance of the Svoboda-Nadler-Vora algorithm for exact multiple-output boolean function minimization is studied and compared with a heuristic minimization method. For this purpose, the algorithm has been implemented in optimized ANSI C code. This implementation introduces a new set of procedures to reduce the cost of prime implicant generation. The concept of weight as the number of 1 and don't care neighbors of a state is used to take advantage of the special cases when a state has only one neighbor or no neighbors at all. The cost of prime implicant generation is further reduced by using the fact that the input dependency of any given state is limited by which of its neighbors exist within an output that are 1 's or don't cares. A detailed example illustrates how the heuristic method can fail to find the absolute minimum of a boolean function. / M.S.