The primary metrics associated with a logic gate's performance are speed, power, and area. We define a gate as a specific CMOS transistor level implementation of a particu- lar boolean function in a specific fabrication technology at a constant rail voltage, constant length, and where the ratio of any two transistor widths are constant. Asking how fast a gate switches then is highly situational; it changes with load capacitance, choice of inputs, input slew rate, and the size of the gate. Predicting how much energy the gate consumes depends on the time frame, how many times the gate has switched in this time frame, input selection, input slew rate, load capacitance, and gate width. Logical Effort (LE) predicts gate delay with a simple linear equation: d = t(gh+p). Where g and p are gate and input dependent parameters independent of load size and gate size, and h is the ratio of output ca- pacitance to input capacitance (directly related to gate width), and t is a process dependent conversion factor. The product, gh, then is the delay associated with driving a subsequent gate, and p is the delay of the gate driving itself. The prediction ignores input slew rate and the linear dependence fails for very large values of h, but for input slew rates on the same order as the output slew rate, and for reasonable fan-outs, LE provides remarkably accurate predictions of gate switching time. The methodology goes on to solve for the widths nec- essary for each gate in an arbitrary logic path to minimize delay. Designs can quickly be compared, analyzed and optimized. By breaking down delay into components, one is able to intuitively choose better logic implementations, if parasitic delay is dominating, often a better implementation is one with smaller fan-in gates and less logic depth, if effort delay is dominating then then higher logic depth can lead to faster results. What the method does not do is predict the power consumption ramifications of all of these choices. What about minimizing power on non-critical paths, for instance? To our knowledge, no methodology exists to predict power consumption in a similar fashion. We propose a power prediction methodology, Logical Power (LP), compatible with LE that breaks down power consumption into dynamic, static, and short-circuit com- ponents with linear equations dependent on h. This would allow a compact and efficient way to characterize a gate that scales with its environment, as well as to allow designers optimizing with LE to consider not only the speed ramifications of individual gate sizings but power as well. For instance given a target path delay higher than the theoretical mini- mum predicted by LE, sizings could be chosen with LE and LP that minimize power that still result in meeting the target delay. The other major contribution of this work is a new short-circuit power measurement technique for simulation that more accurately distinguishes between short-circuit and the parasitic portions of dynamic power in total active power dissipation than all known tech- niques.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990. / Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.

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Recently, researchers have been interested in reversible computing because of its ability to dissipate nearly zero heat and because of its applications in quantum computing and low power VLSI design. Synthesis and testing are two important areas of reversible logic. The thesis first presents an approach for the synthesis of reversible circuits from the exclusive- OR sum-of-products (ESOP) representation of functions, which makes better use of shared functionality among multiple outputs, resulting in up to 75% minimization of quantum cost compared to the previous approach. This thesis also investigates the previous work on constructing the online testable circuits and points out some design issues. A simple approach for online fault detection is proposed for a particular type of ESOP-based reversible circuit, which is also extended for any type of Toffoli circuits. The proposed online testable designs not only address the problems of the previous designs but also achieve significant improvements of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively. / xii, 82 leaves : ill. ; 29 cm