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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
41

Power estimation for combinational logic and low power design /

Kim, Dongho. January 2001 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references (leaves 99-104). Available also in a digital version from Dissertation Abstracts.
42

Automated generation of round-robin arbitration and crossbar switch logic

Shin, Eung Seo. January 2003 (has links) (PDF)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Mary Ann Ingram, Committee Member; Lim, Sung Kyu, Committee Member; Riley, George F., Committee Member; Mooney III, Vincent J., Committee Chair; Pande Santosh, Committee Member. Includes bibliography.
43

A programmed test sequence generation to detect and distinguish failures in a combinational circuit

Huang, George Huang-Liang, 1938- January 1973 (has links)
No description available.
44

An efficient single-latch scan-design scheme/

Panda, Uma R. January 1985 (has links)
No description available.
45

Loginių schemų struktūros analizė. VHDL loginių schemų kelių skaičiavimas. Kelių pasiskirstymas schemos realizacijose. Fiktyvių kelių ieškojimas / Structure analysis of combinational logic circuit. Calculating pathways in VHDL combinational logic circuits.Comparing pathways of realizations. Counting the number of fictional pathways in every realization

Lukošius, Tomas 31 May 2004 (has links)
The combinational logic circuits, which are performing some kind of logic function, can have several realizations. Realizations differ from each other, because of the elements of the database used in circuit. The test of one scheme realization do not necessarily fully verify mistakes of the other realization. The number of pathways in different realizations may also differ. The determination of dependence between test's propriety and the number of pathways for different circuits is the main task in this paper. After finding pathways in different realizations of circuit, and comparing these pathways, the number of fictional pathways in every realization is detected. Special software was developed for calculating pathways in VHDL combinational logic circuits. The software was used for testing pathway calculation operations of circuit realization and for comparing pathways of realizations. The main purpose of this paper was to develop software for pathways in VHDL circuit calculation, to perform experiments using this software, and to estimate the dependence for the number of pathways. The practise of developed software is wide. This system may be implemented for optimising the algorithm of test generator. Usually the test generation program generates more than minimum of possible tests. If the number of pathways in circuit is known, the developed software will help to optimise the algorithm of test generation so that the minimum number of tests would be generated.
46

Hazard detection with VHDL in combinational logic circuits with fixed delays /

Chu, Ming-Cheung, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.
47

Discrete state analysis technique for accurate estimation of switching activities /

Lim, Yong Je. January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [90]-94).
48

Hierarchical fault collapsing for logic circuits

Sandireddy, Raja Kiran Kumar Reddy. Agrawal, Vishwani D., January 2005 (has links) (PDF)
Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references (p.68-73).
49

Dynamic logic design and synthesis using clock-delayed domino /

Yee, Gin Sun. January 1999 (has links)
Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (leaves 147-153).
50

An efficient single-latch scan-design scheme/

Panda, Uma R. January 1985 (has links)
No description available.

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