Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system. We propose a low jitter voltage controlled oscillator designed in TSMC 0.35£gm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.

<p>Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance.</p><p>One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle.</p><p>The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.</p>

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations. / Graduation date: 2013

Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle. The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.