This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text

Το αντικείμενο της παρούσας διδακτορικής διατριβής με τίτλο “Σχεδιασμός Κρυπτογραφικών Συστημάτων με Υλικό Ειδικού Σκοπού” είναι ο σχεδιασμός κρυπτογραφικών μηχανισμών για την ενσωμάτωσή τους σε συστήματα περιορισμένων πόρων (κόστος υλικού, καταναλισκόμενη ισχύς, ενέργεια). Πρωταρχικοί στόχοι είναι η περιορισμένη κατανάλωση ισχύος και η ελαχιστοποίηση του κόστους υλικού ενώ ο ρυθμός απόδοσης σε αυτά τα συστήματα αποτελεί δεύτερο στόχο. Σύγχρονα συστήματα όπως έξυπνες κάρτες και RFID ετικέτες δεν έχουν την απαιτούμενη επιφάνεια για να ολοκληρώσουν-ενσωματώσουν μεγάλα συστήματα κρυπτογραφίας άλλα ούτε τους απαραίτητους πόρους σε ενέργεια. Οι κρυπτογραφικές πράξεις είναι από τη φύση τους δύσκολο να αναλυθούν, να απλοποιηθούν και να υλοποιηθούν. Παρόλα αυτά η διδακτορική διατριβή έδειξε ότι μπορεί να εφαρμοστούν σε αυτές τεχνικές χαμηλής κατανάλωσης ισχύος. Αν σε ένα κρυπτογραφικό σύστημα, οι μη αποδοτικές πράξεις από πλευράς κατανάλωσης ισχύος του συνολικού συστήματος μπορεί να αποκτήσουν χαρακτηριστικά χαμηλής κατανάλωσης ισχύος, τότε μειώνεται αισθητά η μέση κατανάλωση ισχύος. Στην προσπάθεια μείωσης της μέσης κατανάλωσης ισχύος των αλγορίθμων είναι ο εντοπισμός των λιγότερο αποδοτικών πράξεων των κρυπτογραφικών συστημάτων και η μελέτη-ανάλυση με σκοπό τη μείωση της κατανάλωσης ισχύος. Επειδή είναι προφανές πως η μεθοδολογία αυτή προορίζεται για συστήματα χαμηλών πόρων πρέπει και το αντίστοιχο κόστος σε υλικό να είναι περιορισμένο. / The evolution of mobile-wireless computing systems have triggered the development of new cryptographic needs. Therefore, existing and new cryptographic algorithm architectures have to be designed in order to satisfy the mobile wireless system specifications. Wireless mobile standards limit a wireless system's throughput to less than a hundred Mbps. This is a quite satisfactory limit and it is capable to support real-time applications as voice, video and online streaming. Additionally, the nature of mobile systems highlights the needs for strict power and area constrains. However, many cryptographic designs focus on achieving high-throughput by unrolling the rounds of the algorithm and using extended pipelining techniques. These designs that can achieve high throughput rates, are appropriate for high-end applications that are not constrained in power consumption and chip covered area. Therefore, it is impossible to integrate these modules in mobile systems. The main contributions of this phd thesis involve: A Lightweight secure mechanism which presents a top-down design methodology. There are three contributions in the domain of optimized cryptographic operations: a) Versatile multiplier for GF(28) Finite Fields, b) Optimized SubBytes transformation in terms of power and area, c) Optimized MixColumns transformation in terms of power and area. Finally an 8-bit Advanced Encryption Standard Design with low power-low area properties is proposed.

The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive. This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator. The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system. To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.

The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA, which was designed explicitly for interfacing with external digital systems. This compatibility creates a streamlined workflow for dropping the FPAA hardware into mixed-signal embedded systems. The second phase, algorithm analysis and modeling, is important to create a useful and reliable library of components for the system designer. We discuss the concept and procedure of analog abstraction that empowers non-circuit design engineers to take full advantage of analog techniques. We use the analog vector-matrix multiplier as an example for a detailed discussion on computational analog analysis and system mapping to the FPAA. Lastly, we describe high-level software tools, which are an absolute necessity for the design of large systems due to the size and complexity of modern FPAAs. We describe the Sim2Spice tool, which allows system designers to develop signal processing systems in the Simulink environment. The tool then compiles the system to the FPAA hardware. By coordinating the development of these three phases, we've created a solid unified framework that empowers engineers to utilize FPAAs.

Micromirror scanners are the most significant of the micro-optical actuator elements with applications in portable digital displays, automotive head-up displays, barcode scanners, optical switches and scanning optical devices in the health care arena for external scanning diagnostics and in vivo scanning diagnostics. Recent development in microscanning technology has seen a shift from conventional electrostatic actuation to electromagnetic actuation mechanisms with major advantages in the ability to produce large scan angles with low voltages, remote actuation, the absence of the pull-in failure mode and the acceptable electrical safety compared to their electrostatic counterparts. Although attempts have been made to employ silicon substrate based MEMS deposition techniques for magnetic materials, the quality and performance of the magnets are poor compared to commercial magnets. In this project, we have developed novel low-cost single and dual-axis polymer hard magnetic micromirror scanners with large scan angles and low power consumption by employing the hybrid fabrication technique of squeegee coating to combine the flexibility of polydimethylsiloxane (PDMS) and the superior magnetic performance of fine particle isotropic NdFeB micropowders. PCB coils produce the Lorentz force required to actuate the mirror for scanning applications. The problem of high surface roughness, low radius of curvature and the magnetic field interaction between the gimbal frame and the mirror have been solved by a part PDMS-part composite fabrication process. Optimum magnetic, electrical and time dependent parameters have been characterized for the high performance operating conditions of the micromirror scanner. The experimental results have been demonstrated to verify the large scan angle actuation of the micromirror scanners at low power consumption.

The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.

abstract: The ubiquity of embedded computational systems has exploded in recent years impacting everything from hand-held computers and automotive driver assistance to battlefield command and control and autonomous systems. Typical embedded computing systems are characterized by highly resource constrained operating environments. In particular, limited energy resources constrain performance in embedded systems often reliant on independent fuel or battery supplies. Ultimately, mitigating energy consumption without sacrificing performance in these systems is paramount. In this work power/performance optimization emphasizing prevailing data centric applications including video and signal processing is addressed for energy constrained embedded systems. Frameworks are presented which exchange quality of service (QoS) for reduced power consumption enabling power aware energy management. Power aware systems provide users with tools for precisely managing available energy resources in light of user priorities, extending availability when QoS can be sacrificed. Specifically, power aware management tools for next generation bistable electrophoretic displays and the state of the art H.264 video codec are introduced. The multiprocessor system on chip (MPSoC) paradigm is examined in the context of next generation many-core hand-held computing devices. MPSoC architectures promise to breach the power/performance wall prohibiting advancement of complex high performance single core architectures. Several many-core distributed memory MPSoC architectures are commercially available, while the tools necessary to effectively tap their enormous potential remain largely open for discovery. Adaptable scalability in many-core systems is addressed through a scalable high performance multicore H.264 video decoder implemented on the representative Cell Broadband Engine (CBE) architecture. The resulting agile performance scalable system enables efficient adaptive power optimization via decoding-rate driven sleep and voltage/frequency state management. The significant problem of mapping applications onto these architectures is additionally addressed from the perspective of instruction mapping for limited distributed memory architectures with a code overlay generator implemented on the CBE. Finally runtime scheduling and mapping of scalable applications in multitasking environments is addressed through the introduction of a lightweight work partitioning framework targeting streaming applications with low latency and near optimal throughput demonstrated on the CBE. / Dissertation/Thesis / Ph.D. Computer Science 2011

La consommation d'énergie des systèmes sur puces induit des contraintes fortes lors de leur conception. Elle affecte la fiabilité du système, le coût du refroidissement de la plateforme, et la durée de vie de la batterie lorsque le circuit est alimenté par des batteries. En fait, avec la diminution de la tailles de la technologie des semi-conducteurs, l'optimisation de la puissance consommée est devenue un enjeu majeur, au même titre que le coût lié à la surface silicium et l'optimisation des performances, en particulier pour les applications mobiles. Des puces codec vidéo dédiées ont été utilisés dans diverses applications telles que les systèmes de vidéoconférence, de sécurité et de surveillance, ou encore et des applications de divertissement. Pour répondre aux contraintes des applications mobiles en termes de performance et de consommation énergétique, le codec vidéo est généralement implémenté en matériel plutôt qu'en logiciel, ce qui permet de garantir les contraintes d'efficacité énergétique et de traitement en temps réel. L'une des normes les plus efficaces pour les applications vidéo est aujourd'hui la norme H.264 Encodage Vidéo Avancé (H.264/AVC), qui offre une meilleure qualité vidéo à un débit binaire plus bas que les normes précédentes. Pour pouvoir effectivement intégrer cette norme dans des produits commerciaux, en particulier pour les appareils mobiles, lors de la conception du codec vidéo en matériel, les concepteurs devront utiliser des approches spécifiques de conception de circuits basse consommation et implanter des mécanismes de contrôle de la consommation. Cette thèse de doctorat s'est déroulée dans le cadre de la conception de l'encoder matériel au format H.264, appelé plateforme VENGME. La plateforme est découpée en différents modules et le module EC-NAL a été développé durant la thèse, en prenant en compte différentes solutions apparues dans la littérature pour minimiser la consommation de ce module. Les résultats en simulation montrent que le module EC-NAL présente de meilleurs résultats d'un point de vue consommation que ses concurrents de la littérature. L'architecture de la plateforme VENGME a ensuite été analysée, et des simulations au niveau RTL ont été menées pour évaluer sa consommation globale. Il en est ressorti une possibilité de diminuer encore plus la consommation de la plateforme matérielle en contrôlant la fréquence de certains modules. Cette approche a été appliquée au module EC-NAL qui possède en interne une FIFO. Dont le niveau peut être contrôlé en ajustant la fréquence d'horloge du côté du sous-module NAL. Cela a donc conduit à implémenter une approche d'adaptation automatique de la fréquence en fonction du niveau de remplissage de la FIFO. Le contrôleur a été implémenté en matériel et la stabilité du système bouclé a été étudiée. Les résultats en simulation montrent l'intérêt de la démarche adoptée qui devra être étendue à l'ensemble de la plateforme. / Power consumption for Systems-on-Chip induces strong constraints on their design. Power consumption affects the system reliability, cooling cost, and battery lifetime for Systems-on-Chips powered by battery. With the pace of semiconductor technology, power optimization has become a tremendous challenging issue together with Silicon area and/or performance optimization, especially for mobile applications. Video codec chips are used in various applications ranging for video conferencing, security and monitoring systems, but also entertainment applications. To meet the performance and power consumptions constraints encountered for mobile applications, video codecs are favorably preferred to be implemented in hardware rather than in software. This hardware implementation will lead to better power efficiency and real-time requirements. Nowadays, one of the most efficient standards for video applications is the H.264 Advanced Video Coding (H.264/AVC) which provides better video quality at a lower bit-rate than the previous standards. To bring the standard into commercial products, especially for hand-held devices, designers need to apply design approaches dedicated to low-power circuits. They also need to implement mechanisms to control the circuit power consumption. This PhD thesis is conducted in the framework of the VENGME H.264/AVC hardware encoder design. The platform is split in several modules and the VENGME Entropy Coder and bytestream Network Abstraction Layer data packer (EC-NAL) module has been designed during this PhD thesis, taking into account and combining several state-of-the-art solutions to minimise the power consumption. From simulation results, it has been seen that the EC-NAL module presents better power figures than the already published solutions. Then, the VENGME H.264 encoder architecture has been analyzed and power estimations at RTL level have been performed to extract the platform power figures. Then, from these power figures, it has been decided to implement power control on the EC-NAL module. This latter contains a FIFO whose level can be controlled via an appropriate scaling of the clock frequency on the NAL side, which leads to the implementation of a Dynamic Frequency Scaling (DFS) approach based on the control of the FIFO occupancy level. The control law has been implemented in hardware (full-custom) and the closed-loop system stability has been studied. Simulation results show the effectiveness of the proposed DVS strategy that should be extended to the whole H.264 encoder platform.

The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test quality is studied by determining the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit design. Given the synthesizable HDL code, the proposed technique will efficiently identify infeasible paths, subsequently, it determines the worst case execution time (WCET) in the HDL code.

abstract: Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microprocessors. These microprocessors are integrated as the major components in many modern embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-known hardware capabilities offered by modern embedded processors. However, the power or thermal aware performance optimization is not fully explored for the mainstream embedded processors with discrete DVFS and DPM capabilities. Many key problems have not been answered yet. What is the maximum performance that an embedded processor can achieve under power or thermal constraint for a periodic application? Does there exist an efficient algorithm for the power or thermal management problems with guaranteed quality bound? These questions are hard to be answered because the discrete settings of DVFS and DPM enhance the complexity of many power and thermal management problems, which are generally NP-hard. The dissertation presents a comprehensive study on these NP-hard power and thermal management problems for embedded processors with discrete DVFS and DPM capabilities. In the domain of power management, the dissertation addresses the power minimization problem for real-time schedules, the energy-constrained make-span minimization problem on homogeneous and heterogeneous chip multiprocessors (CMP) architectures, and the battery aware energy management problem with nonlinear battery discharging model. In the domain of thermal management, the work addresses several thermal-constrained performance maximization problems for periodic embedded applications. All the addressed problems are proved to be NP-hard or strongly NP-hard in the study. Then the work focuses on the design of the off-line optimal or polynomial time approximation algorithms as solutions in the problem design space. Several addressed NP-hard problems are tackled by dynamic programming with optimal solutions and pseudo-polynomial run time complexity. Because the optimal algorithms are not efficient in worst case, the fully polynomial time approximation algorithms are provided as more efficient solutions. Some efficient heuristic algorithms are also presented as solutions to several addressed problems. The comprehensive study answers the key questions in order to fully explore the power and thermal management potentials on embedded processors with discrete DVFS and DPM capabilities. The provided solutions enable the theoretical analysis of the maximum performance for periodic embedded applications under power or thermal constraints. / Dissertation/Thesis / Ph.D. Computer Science 2012