Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution under continuous solution space. However, it is more complex to use Lagrangian relaxation under discrete solution space. The Lagrangian dual problem is non-convex and previously a sub-gradient method was used to solve it. The sub-gradient method is a greedy approach for substituting gradient method in the deepest descent method, and has room for further improvement. In addition, Lagrangian sub-problem cannot be solved directly by mathematical approaches under discrete solution space. Here we propose a new Lagrangian relaxation-based method for simultaneous gate sizing and Vt assignment under discrete solution space. In this work, some new approaches are provided to solve the Lagrangian dual problem considering not only slack but also the relationship between Lagrangian multipliers and circuit timing. We want to solve the Lagrangian dual problem more precisely than did previous methods, such as the sub-gradient method. In addition, a table-lookup method is provided to replace mathematical approaches for solving the Lagrangian sub-problem under discrete size and Vt options. The experimental results show that our method can lead to about 50 percent and 58 percent power reduction subject to the same timing constraints compared with a Lagrangian relaxation method using sub-gradient method and a state-of-the-art previous work. These two methods are implemented by us for comparison. Our method also results in better circuit timing subject to tight timing constraints.

This thesis discusses the implementation of a digital signal processor (DSP), including the DSP core and the peripheral interfaces. The DSP core includes three parallel computational units (arithmetic/logic unit, multiplier/accumulator, and barrel shifter), two independent data address generators, and a powerful program sequencer. The I/O designs provide two kinds of interfaces: serial ports and direct memory access (DMA) ports. The DMA contains two modes: full memory mode and host mode. To reduce power consumption in the instruction memory access, we add an instruction buffer for nested loops where the instructions in a loop are fetched only once and then put into the instruction buffer to be used in the subsequent iterations. The DSP implementation has passed the verification procedures both in the front-end synthesis by Synopsys Design Compiler and the back-end post-layout simulation by Nanosim. Furthermore, some benchmark DSP application programs such as FFT, FIR, and DCT are executed on the implemented DSP core.

The first topic of this thesis is to propose a design of an all-digital low¡Vpower PLL (ADPLL). This design is implemented by only using standard cell library. The design cycle is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly raised. The large power consumption, glitch hazards, and timing violations of prior ADPLL designs are avoided by the proposed control method and modified DCO with multiplexers. The proposed design is implemented by only using the standard cell library of TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um 1P6M CMOS process. The feature of power saving is verified by measurement, which shows that the power consumption of the proposed ADPLL is merely 1.45 mW at 166 MHz output. The second topic of this thesis is a load shift keying wireless modulator circuit for implantable biomedical SOC. We successfully realize data and power transmission between outer controller and an implantable chip via wireless RF transmission interface. The convenience and the safety of using the implantable biomedical chip are significantly improved. The proposed on-chip LSK modulator consumes less power and area than those of traditional designs. Hence, the design margin of the implantable biomedical chip will be relaxed. The proposed LSK modulator is implemented with TSMC 0.35um 2P4M mixed-signal process. The proposed wireless RF transmission interface is implemented on PCB with discrete components.

Since the development of SoC is very fast, how to reduce the power consumption of SoC has become a very important issue. To overcome the issue, the hardware circuit provides multi-voltage method to reduce task power consumption. On the other hand, the software tool decides the task voltage to minimize the total power consumption. In this thesis, we developed a genetic algorithm to solve the voltage mapping problem of multi-voltage systems. This goal of this genetic algorithm is to consider the time constraints or power constraints in the multi-voltage system to find the better solution. In order to apply genetic algorithm to solve voltage mapping problem, we build a compilation flow that embeds in the genetic algorithm. To demonstrate the efficiency of proposed approach, we apply compilation flow to two examples. One is multi-voltage reconfigurable processor system. The processor in the system provides multi-mode and multi-voltage. The multi-mode can reduce the execution time of tasks with high parallelism. Multi-voltage can reduce the power consumption of task by decreasing voltage. We use genetic algorithm to choose task mode to achieve the performance goal. Another is multiple multi-voltage processors. We use list-scheduling to find the task schedule and use genetic algorithm to choose the task voltage. This method can reduce total power consumption. According to the experimental results, the proposed genetic algorithm can reduce the power consumption efficiently.

In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates with Hspice. According to the simulation results, the proposed design can obtain power saving around 15% more than conventional multipliers, although it must occupy larger area.

The first topic of this thesis is a C-less and R-less ASK (Amplitude Shift Keying) demodulator design for wireless implantable devices. Lots of prior ASK demodulators were composed of one or more capacitors which might be integrated in a chip or positioned off-chip on a PCB (Printed Circuit Board). The capacitor increases the area of the implantable system regardless of on-chip or off-chip, which violates the small-scale requirement for implanted applications. Thus, this work proposes a miniature ASK demodulator without any passive elements, i.e., R or C. The noise margin of the envelope detector in the C-less ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12. The second topic of this thesis is a design of a low-power 2-dimensional bypassing multiplier. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 41% compared to the prior design with obscure penalty of delay and area.

A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.

The digital product increases widely and vastly. We need a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). In most ADC structure there have an important building block called the front-end sample-and-hold circuit (SHA) . I will design and implement a high speed and low power sample and hold circuit. In this thesis, the circuits are designed with UMC 90nm 1P9M CMOS process and 1.2V of supply voltage. The speed and resolution of SHA are 100Ms/s and 10bits individually. The circuit is implemented with class AB amplifier.

The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to the desktop, the consumers will expect high-quality 3D experience, and this is a big challenge. Handheld devices have slower processors that are less capable of computing large workloads, and the batteries have limited lifetimes, so for large and complex workload, we need an excellent power management policy for saving power. Besides, although mobile platforms have lower resolution than desktop, each pixel must still be rendered since the screen is closed to the observer¡¦s eye, or we will see some imperfections. For the reasons above, we make a point of performance optimization and power saving, and these rely on accuracy and fast workload estimation. We refer to some workload estimation methods which researchers have mentioned before, such as UW1, UW5, PID[8], Frame Structure[9], Signature Table[1], and hybrid power management policy[10].UW1 and UW5 both use the previous workload as the estimation workload. PID uses the feedback loop to correct the estimation workload. Frame Structure classifies frames into several structures, and sums the workload of each structure up as the estimation workload. Signature Table stores some 3D parameters in the table, and when a new frame comes in, the 3D parameters of this frame will compare with the table, if match, we use the workload in the table as the estimation workload. Our method is a hybrid policy of UW1 and UW5, and we will decide to use UW1 or UW5 when a new frame comes in. Finally we will compare the performance of each power management policy.

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption. In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers. In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers. In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early. In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery¡¦s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.