In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion

In this thesis, the possibility of harvesting energy from a multicore power cableconnected to a power outlet is presented and evaluated. By surrounding a powercable with a conductive material connected to ground, it is shown that the dif-ference in potential between the power cable and the conductive material causesa capacitance which can charge a capacitor that in combination with an energymanagement circuit can be used to wirelessly transmit data with an interval de-pending on factors like the length of the surrounding material and the type ofcable it is placed around. In addition to this, a technique to, in a non-invasiveway, sense whether there is alternating current flowing in a multicore power ca-ble is brought up. The results show that this technique can be used to detectalternating current without having a device connected between the power cableand the power outlet. These two sections combined are used to design a surveil-lance system that should monitor consumer electronics in the home environmentwhere there is a fire hazard. The system should send out a warning signal thatis visible for the homeowner to remind the user to switch off the power of theelectronic devices before leaving home.

A clock driver that works on the principle of charging and discharging the clock network in a VLSI circuit in two steps is investigated in a few different configurations. The aim of the design is twofold: to reduce the power consumption to reduce the third harmonic of the clock signal, and thereby the EMI (electromagnetic interference) emitted by the clock network. The first should be possible to accomplish as the clock interconnect network gets charged by half the voltage during each rising transition, and the second should be possible to accomplish by carefully time the rising and falling transitions, so that the third Fourier coefficient of the resulting wave form cancels. The drivers are loaded by eight 16-bit adders. The drivers’ power consumption, and the spectrum of the output signal, are investigated under varying clock frequencies, power supply voltage, and driver architecture. The results are compared to a conventional square wave clock. The results are that while the third harmonics of the resulting output sees an improvement in all the investigated cases over the square wave clock, the power savings are, for higher clock frequencies, more than completely canceled by the extra power needed in the logic stage which controls these drivers. On the other hand, the power consumption of the new driver appears to drop below that of the conventional driver when the clock frequency drops below approximately 100MHz. A few suggestions for further investigations of new designs and clock wave forms are given.

Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity. The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter. By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 73-75).

Thesis (ME--Engineering) -- AUT University, 2009. / Includes bibliographical references. Also held in print (131 leaves : ill. ; 30 cm. + 1 CD-ROM) in the Archive at the City Campus (T 621.384 PRI)

abstract: In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24]. First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area. Our implementation of the 2D DCT has comparable PSNR performance with respect to the algorithm presented in [23] with ~35-50% reduction in area. Next, we use the approximate 2x2 multiplier presented in [24] to implement parallel approximate multipliers. We demonstrate that if some of the 2x2 multipliers in the design of the parallel multiplier are accurate, the accuracy of the multiplier improves significantly, especially when two large numbers are multiplied. We choose Gaussian FIR Filter and Fast Fourier Transform (FFT) algorithms to illustrate the efficacy of our proposed approximate multiplier. We show that application of the proposed approximate multiplier improves the PSNR performance of 32x32 FFT implementation by 4.7 dB compared to the implementation using the approximate multiplier described in [24]. We also implement a state-of-the-art image enlargement algorithm, namely Segment Adaptive Gradient Angle (SAGA) [29], in hardware. The algorithm is mapped to pipelined hardware blocks and we synthesized the design using 90 nm technology. We show that a 64x64 image can be processed in 496.48 µs when clocked at 100 MHz. The average PSNR performance of our implementation using accurate parallel adders and multipliers is 31.33 dB and that using approximate parallel adders and multipliers is 30.86 dB, when evaluated against the original image. The PSNR performance of both designs is comparable to the performance of the double precision floating point MATLAB implementation of the algorithm. / Dissertation/Thesis / M.S. Computer Science 2013

Made available in DSpace on 2014-06-12T15:58:17Z (GMT). No. of bitstreams: 2 arquivo3360_1.pdf: 1861373 bytes, checksum: da4095d44ee2bf2199c241b47e6516e9 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010 / Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às tendências de mercado atuais, dispositivos portáteis, alimentados à bateria, estão sendo cada vez mais procurados, de modo que uma demanda de produtos que tenham uma maior capacidade de prolongar a vida útil das baterias vem crescendo. Recentemente, a redução do tamanho do transistor propiciou uma mudança no comportamento das componentes de energia em transistores CMOS. A componente estática que antigamente era praticamente desprezada tem aumentado exponencialmente com alterações não proporcionais, tais como diminuição do canal e redução de tensão de alimentação dos circuitos. Atualmente, esta componente estática representa uma fração significante da potência total consumida em circuitos com tecnologias de fabricação abaixo de 90 nm, podendo passar de 50% da potência total. Este consumo torna-se cada vez mais expressivo à medida que as tensões de alimentação dos circuitos são reduzidas, devido à necessidade de se minimizar a tensão de threshold para manter o desempenho dos circuitos. O algoritmo desenvolvido para a redução de potência estática em circuitos integrados digitais pode ser inserido no fluxo de desenvolvimento, sem causar penalidades ao mesmo. Na abordagem proposta, baseada na técnica Dual-Threshold, parte das células do circuito é substituída por células com tensão de threshold mais alta sem que haja inserção de violações de tempo no circuito. A troca de cada célula é definida a partir de estimativas do comportamento do circuito caso a célula seja trocada, antes que ela seja de fato substituída. Ao contrário de abordagens baseadas em caminhos, a característica de não haver trocas a cada análise das células do circuito, permite uma redução significativa no tempo de execução do algoritmo. Os resultados obtidos, que apresentaram uma redução de potência estática de até 39%, resultaram da execução do algoritmo utilizando circuitos do benchmark ISCAS85

Pervasive Service Discovery (SD) in Low-power and Lossy Networks (LLNs) is expected to play a major role in realising the Internet of Things (IoT) vision. Such a vision aims to expand the current Internet to interconnect billions of miniature smart objects that sense and act on our surroundings in a way that will revolutionise the future. The pervasiveness and heterogeneity of such low-power devices requires robust, automatic, interoperable and scalable deployment and operability solutions. At the same time, the limitations of such constrained devices impose strict challenges regarding complexity, energy consumption, time-efficiency and mobility. This research contributes new lightweight solutions to facilitate automatic deployment and operability of LLNs. It mainly tackles the aforementioned challenges through the proposition of novel component-based, automatic and efficient SD solutions that ensure extensibility and adaptability to various LLN environments. Building upon such architecture, a first fully-distributed, hybrid pushpull SD solution dubbed EADP (Extensible Adaptable Discovery Protocol) is proposed based on the well-known Trickle algorithm. Motivated by EADPs’ achievements, new methods to optimise Trickle are introduced. Such methods allow Trickle to encompass a wide range of algorithms and extend its usage to new application domains. One of the new applications is concretized in the TrickleSD protocol aiming to build automatic, reliable, scalable, and time-efficient SD. To optimise the energy efficiency of TrickleSD, two mechanisms improving broadcast communication in LLNs are proposed. Finally, interoperable standards-based SD in the IoT is demonstrated, and methods combining zero-configuration operations with infrastructure-based solutions are proposed. Experimental evaluations of the above contributions reveal that it is possible to achieve automatic, cost-effective, time-efficient, lightweight, and interoperable SD in LLNs. These achievements open novel perspectives for zero-configuration capabilities in the IoT and promise to bring the ‘things’ to all people everywhere.

This diploma thesis deals with the design of low-power IoT device communicating by using the NB-IoT standard. The theoretical part of the thesis is dedicated to the explanation of the principles and capabilities of communication in IoT networks Sigfox, LoRa and NB-IoT, and also its physical layer, network architecture, techonology principles and frequency bands used. The application part of the thesis is dedicated to design of the NB-IoT device from the system design through the selection of main components to the detailed physical design of the device. Two prototypes of the device with two different radio modules used are fabricated on which is performed measurement of the power profile of the device in various operation modes.