Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.

In this thesis, we propose a circuit design technique that reduces the energy utilized by any logic circuit for computation. We achieve this, by reducing the voltage swing on the circuit without greatly compromising the speed of operation and keeping in mind the noise margin constraints. Our technique involves the use of head or tail transistors that provide a Vth drop in the voltage swing. We choose to use head or tail transistors on alternate logic levels providing us with an option of driver stage, based on the noise margin of the subsequent stage. We demonstrate the working of this concept on inverter chains, to prove the correctness as well as the ability of the reduced voltage swing circuits to drive subsequent stages. We also discuss the implementation of this technique on basic gates and simple combinational circuits. We then show detailed experiments on a larger circuit, in this case a Kogge-Stone parallel prefix adder. We will discuss the overheads involved in the design and methods to partially overcome these by the use of selectively skewed gates and application of forward body bias. Finally we implement the same design using a different technology to demonstrate the scalability of the technique. / text

Mak Wing-sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaf [68]). / Abstracts in English and Chinese. / List of Figures --- p.I / List of Tables --- p.III / ACKNOWLEDGMENTS / ABSTRACT / Chapter Chapter I --- Introduction / Chapter 1.1 --- Introduction - Low Power --- p.I-1 / Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1 / Chapter 1.2.1 --- Static Power Dissipation --- p.I-2 / Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5 / Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8 / Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10 / Chapter 1.4 --- Objective of the Project --- p.I-10 / Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic / Chapter 2.1 --- Low Power Design --- p.II-12 / Chapter 2.2 --- Adiabatic Switching --- p.II-12 / Chapter 2.3 --- Adiabatic Logic --- p.II-14 / Chapter 2.4 --- History of Adiabatic Logic --- p.II-17 / Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter / Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18 / Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20 / Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22 / Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23 / Chapter Chapter IV --- Power Clock Generator / Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24 / Chapter 4.2 --- Power Clock Generator / Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV / Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27 / Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier / Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32 / Chapter 5.2 --- Structure of Multiplier --- p.V-34 / Chapter Chapter VI --- Simulations / Chapter 6.1 --- AqsCMOS Inverter / Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38 / Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39 / Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI / Chapter 6.2 --- Power Clock Generator --- p.VI -42 / Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45 / Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46 / Chapter ChapterVII --- evaluations / Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51 / Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus / Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54 / Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55 / Chapter 7.2.3 --- Input Current Measurement --- p.VII -58 / Chapter 7.3 --- Power Measurement --- p.VII -63 / Chapter Chapter VIII --- Conclusions and Fiirthfr Developments / Chapter 8.1 --- Conclusions --- p.VIII -65 / Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65 / Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65 / Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66 / Chapter 8.2 --- Further Development --- p.VIII -66 / Appendix I micro-photography of aqscmos multiplier / Appendix II micro-Photography of CMOS multiplier / Appendix III micro-photography of AqsCMOS inverter chain testing modules / Appendix IV power - meter simulation approach / Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers / Reference

by Kelvin Cheung Ka Wai. / Thesis submitted in: June 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / ACKNOWLEDGEMENTS --- p.i / ABSTRACT --- p.ii / TABLE OF CONTENTS --- p.iii / LIST OF FIGURES --- p.vi / TIST OF TABLES --- p.viii / Chapter 1. --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Objective --- p.1-1 / Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1 / Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1 / Chapter 1.3.2 --- Dynamic logic --- p.1-2 / Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4 / Chapter 1.4.1 --- Static power dissipation --- p.1 -4 / Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6 / Chapter 1.4.2.1 --- Short circuit current --- p.1 -6 / Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6 / Chapter 1.4.2.3 --- Total power consumption --- p.1-8 / Chapter 1.5 --- Adiabatic Logic --- p.1-8 / Chapter 1.5.1 --- Low power electronics --- p.1-8 / Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9 / Chapter 1.6 --- Resources --- p.1-10 / Chapter 1.6.1 --- Computing instrument --- p.1-10 / Chapter 1.6.2 --- CAD tools --- p.1-10 / Chapter 1.6.3 --- Fabrication --- p.1-11 / Chapter 1.7 --- Organisation of the Thesis --- p.1-11 / Chapter 2. --- BACKGROUND THEORIES --- p.2-1 / Chapter 2.1 --- Limit of energy dissipation --- p.2-1 / Chapter 2.2 --- Reversible Electronics --- p.2-1 / Chapter 2.2.1 --- Reversibility --- p.2-1 / Chapter 2.2.2 --- Adiabatic Switching --- p.2-3 / Chapter 2.2.2.1 --- Conventional Charging --- p.2-3 / Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4 / Chapter 2.2.3 --- Reversible devices --- p.2-5 / Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6 / Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1 / Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1 / Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1 / Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2 / Chapter 3.2 --- Redistribution of Charge --- p.3-3 / Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4 / Chapter 3.3.1 --- False reversible inverter --- p.3-4 / Chapter 3.3.2 --- Adiabatic inverter --- p.3-5 / Chapter 3.3.3 --- Effective capacitance --- p.3-7 / Chapter 3.3.4 --- Logic alignment --- p.3-8 / Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10 / Chapter 3.3.5.1 --- Compensated cascading --- p.3-10 / Chapter 3.3.5.2 --- Balanced cascading --- p.3-11 / Chapter 3.4 --- Frequency Control --- p.3-12 / Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13 / Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1 / Chapter 4.1 --- Design --- p.4-1 / Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1 / Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2 / Chapter 4.1.3 --- Layout --- p.4-3 / Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3 / Chapter 4.1.3.2 --- Transistor pair --- p.4-9 / Chapter 4.2 --- Capacitance Calculation --- p.4-9 / Chapter 4.2.1 --- Non-switching device --- p.4-10 / Chapter 4.2.2 --- Switching device --- p.4-11 / Chapter 4.3 --- Clocking Scheme --- p.4-13 / Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14 / Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1 / Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2 / Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3 / Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4 / Chapter 5.3.1 --- Transistor sizing --- p.5-5 / Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5 / Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6 / Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6 / Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7 / Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9 / Chapter 6. --- EVALUATION --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Simulation Results --- p.6-1 / Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1 / Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4 / Chapter 6.2.2.1 --- Functional evaluation --- p.6-4 / Chapter 6.2.2.2 --- Performance evaluation --- p.6-6 / Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8 / Chapter 6.3.1 --- Layout --- p.6-8 / Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10 / Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11 / Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13 / Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14 / Chapter 6.3.5.1 --- DC characteristics --- p.6-14 / Chapter 6.3.5.2 --- AC characteristics --- p.6-14 / Chapter 6.3.6 --- Power dissipation --- p.6-17 / Chapter 7 --- CONCLUSIONS --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Design --- p.7-1 / Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1 / Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2 / Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2 / Chapter 7.3 --- Function --- p.7-3 / Chapter 7.4 --- Power Dissipation --- p.7-3 / Chapter 7.5 --- Discussion --- p.7-3 / Chapter 7.6 --- Further Development --- p.7-3 / Chapter 7.7 --- Conclusion --- p.7-4 / Chapter 8. --- REFERENCES --- p.8-1 / APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1 / APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.05𝑚𝑚2 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net 𝐹𝑂𝑀𝐴 of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is > 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator.

by Cheng Wang Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 108-111). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgments --- p.v / Contents --- p.vii / List of Tables --- p.xiii / List of Figures --- p.xiv / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2 / Chapter 1.3 --- General Background --- p.2 / Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4 / Chapter 1.4 --- Research Goal --- p.4 / Chapter 1.5 --- Thesis Outline --- p.5 / Chapter Chapter2 --- RF Fundamentals --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Frequency Translation --- p.6 / Chapter 2.3 --- Conversion Gain --- p.8 / Chapter 2.4 --- Linearity --- p.8 / Chapter 2.4.1 --- 1-dB Compression Point --- p.11 / Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11 / Chapter 2.5 --- Dynamic Range (DR) --- p.13 / Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13 / Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14 / Chapter 2.6 --- Blocking and Desensitization --- p.15 / Chapter 2.7 --- Port-to-Port Isolation --- p.15 / Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16 / Chapter 2.9 --- Noise --- p.16 / Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17 / Chapter 2.9.2 --- Noise Figure --- p.18 / Chapter Chapter3 --- Downconversion Mixer --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Review of Mixer Topology --- p.19 / Chapter 3.2.1 --- Square-Law Mixer --- p.20 / Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21 / Chapter 3.2.3 --- Potentiometric Mixer --- p.22 / Chapter 3.2.4 --- Subsampling Mixer --- p.23 / Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24 / Chapter 4.1 --- Analysis of Proposal Mixer --- p.24 / Chapter 4.2 --- Current Folded Mirror Mixer --- p.24 / Chapter 4.2.1 --- Operating Principle --- p.25 / Chapter 4.2.2 --- Large Signal Analysis --- p.26 / Chapter 4.2.3 --- Small Signal Analysis --- p.29 / Chapter 4.3 --- Current Mode Mixer --- p.32 / Chapter 4.3.1 --- Operating Principle --- p.33 / Chapter 4.3.2 --- Large Signal Analysis --- p.33 / Chapter 4.3.3 --- Small Signal Analysis --- p.34 / Chapter 4.3.4 --- V-I Converter --- p.36 / Chapter 4.3.4.1 --- Equation Analysis --- p.37 / Chapter 4.4 --- Second Order Effects --- p.38 / Chapter 4.4.1 --- Device Mismatch --- p.38 / Chapter 4.4.2 --- Body Effect --- p.39 / Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39 / Chapter 4.6 --- Output Buffer Stage --- p.40 / Chapter 4.7 --- Noise Theory --- p.41 / Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42 / Chapter 4.7.2 --- Noise Figure --- p.43 / Chapter Chapter5 --- Simulation Results --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Current Folded Mirror Mixer --- p.44 / Chapter 5.2.1 --- Conversion Gain --- p.45 / Chapter 5.2.2 --- Linearity --- p.46 / Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49 / Chapter 5.2.3 --- Output Buffer Stage --- p.49 / Chapter 5.3 --- Current Mode Mixer --- p.51 / Chapter 5.3.1 --- Conversion Gain --- p.51 / Chapter 5.3.2 --- Linearity --- p.52 / Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52 / Chapter 5.3.3 --- Output Buffer Stage --- p.53 / Chapter 5.3.4 --- V-I Converter --- p.54 / Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55 / Chapter Chapter6 --- Layout Consideration --- p.57 / Chapter 6.1 --- Introduction --- p.57 / Chapter 6.2 --- CMOS transistor Layout --- p.57 / Chapter 6.3 --- Resistor Layout --- p.59 / Chapter 6.4 --- Capacitor Layout --- p.60 / Chapter 6.5 --- Substrate Tap --- p.62 / Chapter 6.6 --- Pad Layout --- p.63 / Chapter 6.7 --- Analog Cell Layout --- p.64 / Chapter Chapter7 --- Measurements --- p.65 / Chapter 7.1 --- Introduction --- p.65 / Chapter 7.2 --- Downconversion mixer --- p.66 / Chapter 7.3 --- PCB Layout --- p.66 / Chapter 7.4 --- Test Setups --- p.68 / Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68 / Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70 / Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72 / Chapter 7.5.1 --- S-Parameter Measurement --- p.75 / Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77 / Chapter 7.5.3 --- 1-dB Compression Point --- p.78 / Chapter 7.5.4 --- IIP3 --- p.79 / Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81 / Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82 / Chapter 7.5.7 --- Discussion --- p.83 / Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84 / Chapter 7.6.1 --- S-Parameter Measurement --- p.87 / Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89 / Chapter 7.6.3 --- 1-dB Compression Point --- p.90 / Chapter 7.6.4 --- IIP3 --- p.91 / Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93 / Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94 / Chapter 7.6.7 --- Discussion --- p.95 / Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96 / Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97 / Chapter 7.7.2 --- Phase Difference Measurement --- p.98 / Chapter 7.7.3 --- Discussion --- p.99 / Chapter Chapter8 --- Conclusion --- p.100 / Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102 / Chapter A.1 --- Large-Signal Analysis --- p.102 / Chapter Appendix B --- Characteristics of the V-I Converter --- p.105 / Chapter B.1 --- Large-Signal Analysis --- p.105 / Bibliography --- p.108

Qian, Zaichen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 62-67). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Methodology --- p.1 / Chapter 1.2 --- Low Power Design --- p.6 / Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10 / Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11 / Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12 / Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15 / Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16 / Chapter 1.4.2 --- Dynamic Power Management --- p.20 / Chapter 1.5 --- Thesis Contribution and Organization --- p.22 / Chapter 2 --- Multi-Voltage Floorplan Design --- p.24 / Chapter 2.1 --- Introduction --- p.24 / Chapter 2.2 --- Problem Formulation --- p.26 / Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29 / Chapter 2.3.1 --- Branching Rules --- p.30 / Chapter 2.3.2 --- Upper Bounds --- p.31 / Chapter 2.3.3 --- Lower Bounds --- p.32 / Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33 / Chapter 2.4 --- Floorplanning --- p.35 / Chapter 2.5 --- Experimental Results --- p.36 / Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37 / Chapter 2.5.2 --- Floorplanning Results --- p.38 / Chapter 3 --- Low Power Scheduling at System Level --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Problem Formulation --- p.42 / Chapter 3.3 --- An Optimal Offline Algorithm --- p.43 / Chapter 3.4 --- Online Algorithm --- p.46 / Chapter 3.4.1 --- Analysis on One Single Interval --- p.46 / Chapter 3.4.2 --- Online Algorithm --- p.49 / Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52 / Chapter 3.5 --- Experimental Results --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.60 / Bibliography --- p.67

Jiang, Mingqi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves [49]-51). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- REWIRE --- p.6 / Chapter 2.2 --- GBAW --- p.7 / Chapter 3 --- Retiming --- p.9 / Chapter 3.1 --- Min-Clock Period Retiming --- p.9 / Chapter 3.2 --- Min-Area Retiming --- p.17 / Chapter 3.3 --- Retiming for Low Power --- p.18 / Chapter 3.4 --- Retiming with Interconnect Delay --- p.22 / Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26 / Chapter 4.1 --- Motivation and Problem Formulation --- p.26 / Chapter 4.2 --- Retiming Indication --- p.29 / Chapter 4.3 --- Target Wire Selection --- p.31 / Chapter 4.4 --- Incremental Placement Update --- p.33 / Chapter 4.5 --- Optimization Flow --- p.36 / Chapter 4.6 --- Experimental Results --- p.38 / Chapter 5 --- Power Analysis for Rewired Retiming --- p.41 / Chapter 5.1 --- Power Model --- p.41 / Chapter 5.2 --- Experimental Results --- p.44 / Chapter 6 --- Conclusion --- p.47 / Bibliography --- p.50

Mok, King Keung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 77-79). / Abstracts in English and Chinese. / Abstract --- p.1 / Contents --- p.5 / List of Figures --- p.7 / List of Tables --- p.10 / Acknowledgments --- p.11 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Low Power Design --- p.12 / Chapter 1.2. --- Power Consumption in Conventional CMOS Logic --- p.13 / Chapter 1.2.1. --- Dynamic Power --- p.13 / Chapter 1.2.2. --- Short-Circuit Power --- p.15 / Chapter 1.2.3. --- Leakage Power --- p.17 / Chapter 1.2.4. --- Static Power --- p.19 / Chapter 1.3. --- Smart Card / RFID --- p.21 / Chapter 1.3.1. --- Applications --- p.21 / Chapter 1.3.2. --- Operating Principle --- p.22 / Chapter 1.3.3. --- Conventional Architecture --- p.23 / Chapter 2. --- Adiabatic Logic --- p.25 / Chapter 2.1. --- Adiabatic Switching --- p.25 / Chapter 2.2. --- Energy Recovery --- p.27 / Chapter 2.3. --- Adiabatic Quasi-Static CMOS Logic --- p.29 / Chapter 2.3.1. --- Logic Structure --- p.29 / Chapter 2.3.2. --- Clocking Scheme --- p.31 / Chapter 2.3.3. --- Flip-flop --- p.33 / Chapter 2.3.4. --- Layout Techniques --- p.38 / Chapter 3. --- Adiabatic RFID --- p.41 / Chapter 3.1. --- System Architecture --- p.41 / Chapter 3.2. --- Circuit Design --- p.42 / Chapter 3.2.1. --- Voltage Limiter --- p.43 / Chapter 3.2.2. --- Substrate Bias Generation Circuit --- p.45 / Chapter 3.2.3. --- Ring Oscillator --- p.46 / Chapter 3.2.4. --- ROM and Control Logic --- p.48 / Chapter 3.2.5. --- Load Modulator --- p.52 / Chapter 3.2.6. --- Experimental Results --- p.53 / Chapter 4. --- Adiabatic Smart Card --- p.59 / Chapter 4.1. --- System Architecture --- p.59 / Chapter 4.2. --- Circuit Design --- p.61 / Chapter 4.2.1. --- ASK Demodulator --- p.61 / Chapter 4.2.2. --- Clock Recovery Circuit --- p.63 / Chapter 4.3. --- Experimental Results --- p.67 / Chapter 5. --- Conclusion --- p.74 / Chapter 6. --- Future Works --- p.76 / Reference --- p.77 / Appendix --- p.80

The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also an important factors in IC development. This thesis investigates some novel techniques for the design of low-power high-performance A/D converters in CMOS technology, and the non-ideal switched-capacitor effects of (SC) circuits. A new successive-approximation A/D converter is proposed with a novel error cancellation scheme. This A/D converter needs only a simple opamp, a comparator, and a few switches and capacitors. It can achieve high resolution with relative low power consumption. A new ratio-independent cyclic A/D converter is also proposed with techniques to compensate for the non-ideal effects. The implementation include a new differential sampling that is used to achieve ratio-independent multiple-by-two operation. Extensive simulations were performed to demonstrate the excellent performance of these data converters. / Graduation date: 1999