Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.

The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.

Το αριθμητικό σύστημα υπολοίπων (RNS) έχει προταθεί ως ένας τρόπος για επιτάχυνση των αριθμητικών πράξεων του πολλαπλασιασμού και της πρόσθεσης. Ένα από τα σημαντικά πλεονεκτήματα της χρήσης του RNS είναι ότι οδηγεί σε κυκλώματα που έχουν το χαρακτηριστικό της χαμηλής κατανάλωσης. Πιο συγκεκριμένα στην παρούσα διατριβή γίνεται μια αναλυτική μελέτη πάνω στην ταχύτητα διεξαγωγής της πράξης του πολλαπλασιασμού και της άθροισης. Ο λόγος που γίνεται αυτό είναι διότι οι εφαρμογές επεξεργασίας σήματος χρησιμοποιούν ιδιαιτέρως τις προαναφερθείσες πράξεις. Επίσης γίνεται μελέτη της ισχύος που καταναλώνεται κατά την επεξεργασία ενός σήματος με τη χρήση των προτεινόμενων αριθμητικών κυκλωμάτων. Ιδιαίτερη έμφαση δίνεται στη χρήση απλών αρχιτεκτονικών τις οποίες μπορούν τα εργαλεία σύνθεσης να διαχειριστούν καλύτερα παράγοντας βέλτιστα κυκλώματα. Τέλος η διατριβή μελετά τα προβλήματα διακύμανσης των παραμέτρων του υλικού που αντιμετωπίζει η σύγχρονη τεχνολογία κατασκευής ολοκληρωμένων κυκλωμάτων. Συγκεκριμένα σε τεχνολογία μικρότερη των 90nm παρατηρείται το φαινόμενο ίδια στοιχεία κυκλώματος να συμπεριφέρονται με διαφορετικό τρόπο. Το φαινόμενο αυτό γίνεται σημαντικά πιο έντονο σε τεχνολογίες κάτω των 45nm. Η παρούσα διατριβή προτείνει λύσεις βασισμένες στην παραλληλία και την ανεξαρτησία των επεξεργαστικών πυρήνων που παρέχει το RNS, για να αντιμετωπίσει το συγκεκριμένο φαινόμενο. / The Residue Number System (RNS) has been proposed as a means to speed up the implementation of multiplication-addition intensive applications, commonly found in DSP. The main benefit of RNS is the inherent parallelism, which has been exploited to build efficient multiply-add structures, and more recently, to design low-power systems. In particular, this dissertation deals with the delay complexity of the multiply-add operation (MAC). The reason for this is that DSP applications are MAC intensive and hence this dissertation proposes solutions to increase the speed of processing. Furthermore, the study of the multiply-add operations is extended to power consumption matters. The dissertation focus on simple architectures such that EDA tools produce efficient in both power and delay, synthesized circuits. Finally the dissertation deals with variability matters that came up as the vlsi technology shrinks below 90nm. Variability becomes unaffordable especially for the 45nm technology node. This dissertation proposes solutions based on parallelism and the independence of the RNS cores to derive variation-tolerant architectures.

Rozšiřování moderních vestavěných a mobilních systémů napájených bateriemi zvyšuje požadavky na návrh těchto systémů s ohledem na příkon. Přestože moderní návrhové techniky optimalizují příkon, elektrická spotřeba těchto obvodů stále roste díky jejich složitosti. Nicméně existuje celá řada aplikací, kde nepotřebujeme získat úplně přesný výstup. Díky tomu se objevuje technika zvaná aproximativní (přibližné) počítání, která umožňuje za cenu zanesení malé chyby do výpočtu významně redukovat příkon obvodů. V práci se zaměřujeme na použití evolučních algoritmů v této oblasti. Ačkoliv již tyto algoritmy byly úspěšně použity v syntéze přesných i aproximativních obvodů, objevují se problémy škálovatelnosti - schopnosti aproximovat složité obvody. Cílem této disertační práce je ukázat, že aproximační logická syntéza založená na genetickém programování umožňuje dosáhnout vynikajícího kompromisu mezi spotřebou a chybou. Byla provedena analýza čtyř různých aplikacích na třech úrovních popisu. Pomocí kartézského genetického programování s modifikovanou reprezentací jsme snížili spotřebu malých obvodů popsaných na úrovni tranzistorů použitelných například v technologické knihovně. Dále jsme zavedli novou metodu pro aproximaci aritmetických obvodů, jako jsou sčítačky a násobičky, popsaných na úrovni hradel. S využitím metod formální verifikace navíc celý návrhový proces umožňuje garantovat stanovenou chybu aproximace. Tyto obvody byly využity pro významné snížení příkonu v neuronových sítích pro rozpoznávání obrázků a v diskrétní kosinově transformaci v HEVC kodéru. Pomocí nové chybové metriky nezávislé na rozložení vstupních dat jsme navrhli komplexní aproximativní mediánové filtry vhodné pro zpracování signálů. Disertační práce reprezentuje ucelenou metodiku pro návrh aproximativních obvodů na různých úrovních popisu, která navíc garantuje nepřekročení zadané chyby aproximace.