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The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and consumer electronics. These smart PICs must rely on the availability of high performance power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are proposed, developed and verified via experimental fabrication. The proposed new process and structure offers superior performance, such as low on-resistance, low gate charge and optimized high breakdown voltage. In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS) process has been applied to the vertical gate structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional UMOS. A specific on-resistance Ron, sp = 60m2·mm2 is observed, which is 45% better than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit (FOM = Ron × Qg) is about 58%. A floating RESURF EDMOS (BV=55V, Ron,sp=36.5m2·mm2) with a 400% improvement in the Safe Operating Area (SOA) when compared to the conventional EDMOS structure is also presented. The proposed EDMOS employs both drain and iii source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device to have better trade-off between breakdown voltage and on-resistance. Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has both horizontal and vertical sections for gate control. This device is implemented in a 0.18?m 30V HV-CMOS process. Compared to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved by 53%.

The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and consumer electronics. These smart PICs must rely on the availability of high performance power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are proposed, developed and verified via experimental fabrication. The proposed new process and structure offers superior performance, such as low on-resistance, low gate charge and optimized high breakdown voltage. In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS) process has been applied to the vertical gate structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional UMOS. A specific on-resistance Ron, sp = 60m2·mm2 is observed, which is 45% better than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit (FOM = Ron × Qg) is about 58%. A floating RESURF EDMOS (BV=55V, Ron,sp=36.5m2·mm2) with a 400% improvement in the Safe Operating Area (SOA) when compared to the conventional EDMOS structure is also presented. The proposed EDMOS employs both drain and iii source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device to have better trade-off between breakdown voltage and on-resistance. Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has both horizontal and vertical sections for gate control. This device is implemented in a 0.18?m 30V HV-CMOS process. Compared to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved by 53%.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck; we must find another way to improve the performance of transistor. In this study, we fully discuss the electrical characteristics and the low temperature effect as the channel of the N-MOSFET being strained. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uni-axial tensile stress. Therefore, we had improved successfully drain current and carrier mobility of NMOS, and the increasing rates are 9% and 12% respectively. In addition, we can understand the influence of low temperature effect on strain silicon by bending silicon substrate with external mechanical stress. It is great that there is no general normal single crystalline silicon to come instead in the change to temperature of Mobility and operate-current. This is this experiment was worth probing into.

Aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) transistors has pushed Si-based transistors to their limit. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Therefore, III-V semiconductor materials have been actively investigated as alternative channel materials, which can extend Moore’s law on CMOS scaling beyond the 22 nm node not only by relying on scaling. Meanwhile, conventional silicon dioxide cannot easily meet the requirement for the scaling of the equivalent oxide thickness; as a result, various high dielectric constant (high-k) materials have been incorporated onto the III-V semiconductor substrate. Nevertheless, the key challenges for high-k/III-V MOSFETs still need to be solved in order to implement high performance high-k/III-V MOSFETs. Those challenges are the lack of high quality and thermodynamically stable insulators that passivate the gate dielectric/III-V interface, compatible III-V p-type MOSFETs, and reliability issue of III-V MOSFETs, etc. The main focus of this dissertation is to develop proper fabrication processes and structures for III-V MOSFETs devices that result in good interface quality and high device performance. Firstly, we studied the effect of interfacial chemistry on ZrO2/InGaAs gate stack comprehensively, comparing ALD ZrO2 with H2O vs. O3 as the oxidizer. We found that the amount of oxygen is critical to form a good interface. Excessive oxygen concentration, e. g. using O3 as the ALD precursor, induces III-V native oxides at the interface. The second part of this dissertation focuses on the III-V MOSFETs with various IPLs. Various IPLs have been demonstrated, for example, a thin PVD Si IPL, and ALD Al2O3, HfAlOx, and ZrAlOx. Those IPLs are demonstrated to be effective interfacial dielectric layers to improve device performance, including frequency dispersion, SS, Ion, effective channel mobility, and reliability. The third part of this study highlights a novel CF4 post-gate plasma treatment on III-V MOSFETs. Fluorine incorporation was demonstrated on various high-k/III-V gate stacks and achieved significant improvements, including Al2O3/In0.53Ga0.47As, Al2O3/InP, HfO2/In0.53Ga0.47As, and HfO2/InP. Detailed physical analysis, electrical characterization and device performance were carried out. With F incorporation, we have successfully developed excellent interface quality of high-k/III-V MOSFETs. As a result, high-performance III-V MOSFETs have been realized. Finally, emerging non-volatile memories, RRAMs, have been demonstrated. We addressed its conducting mechanism by conducting various experiments and purposed a model for SiOx RRAMs: the conducting filament is randomly formed within the SiOx at the sidewall edge, depending on pre-existing defects. Moreover, the rupture/recovery could occur anywhere along the conducting filament, depending on a random process that determines the location of the weak spot along the conducting filament. In addition, we improved SiO2-based RRAM by incorporating a thin silicon layer onto its sidewall. This technique significantly reduced the electroforming voltage and instability of HRS current of SiO2-based RRAMs. Consequently, a tri-state pulse endurance performance over 106 cycles has been demonstrated and the data stored had good read disturb immunity and thermal disturbance. / text

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