Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck; we must find another way to improve the performance of transistor. In this study, we fully discuss the electrical characteristics and the hot carrier effect as the channel of the N-MOSFETs being strained. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uniaxial tensile stress. Therefore, we successfully improve drain current and carrier mobility of NMOS, and the increasing rates are 22% and 30% respectively. In addition, we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress. With the increase of curvature, substrate current goes up. We offer an explanation to verify this result.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find another way to improve the performance of transistor. The reliability is more important in the shorter and shorter device channel. In this study, we fully discuss the electrical characteristics of the hot carrier effect at various temperature of 65nm MOSFETs under external mechanical stress. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uniaxial tensile stress. Therefore, we successfully improve drain current and carrier mobility of NMOS, but the hot carrier effect is more serious. In addition, we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress. With the increase of curvature, substrate current goes up. We offer an explanation to verify this result. The temperature effect is also measured. The drain current and mobility increased with the temperature decreasing, but the substrate current increased with temperature increasing.

As devise sizes approach the nanoscale, novel device geometries and materials are considered, and new types of essential physics becomes important and new physical switching mechanism are considered, and as our intuitive understanding of device behavior is stretched accordingly, increasing first-principles simulation is required to understand and predict device behavior. To this end, initially I worked to capture the richness of the confinement and transport physics in quantum-wire devices. I developed an efficient fully three dimensional atomistic quantum transport simulator within a nearest-neighbor atomistic tight-binding framework. However, I soon adapted this work to the study of transport in graphene mono-layer and bilayer nano-ribbons. Motivated by proposals for use of nano-ribbons to create band gaps in otherwise gapless graphene monolayers, I studied the effects of edge disorder in such graphene nano-ribbon FETs. I found that ribbon widths sufficiently narrow to produce useful bandgaps, would also lead to an extreme sensitivity to ribbon-edge roughness and associated performance degradation and device-to-device variability. Going beyond conventional switching but staying with the graphene material system, to model electron-hole condensation in two graphene monolayers separated by a tunnel dielectric potentially beyond room temperature, I developed a self-consistent atomistic tight-binding treatment of the required interlayer exchange interaction within non-local Hartree-Fock mean-field theory. Such condensation, associated many-body enhanced interlayer current flow, and gate-control thereof is the basis for the beyond-CMOS Bilayer-pseudoSpin Field Effect Transistor (BiSFET) proposed by colleagues. I studied the effect of various system parameters and on interlayer charge imbalance on the strength of the condensate state. I also modeled the critical current, the maximum interlayer current that can be supported by the condensate, its detailed dependence on the nature and strength of the required interlayer bare tunneling and on charge imbalance. The results presented here are expected to be used to refine devices models of the BiSFET, and may serve as guides to experiments to observe such a condensate state. / text

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Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress. For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 µJ and 316.49 µJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates direct-bond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging module's parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 µJ and 238.99 µJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33oC/W and 82oC/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management. To test the breakdown voltage of series-connected power MOSFETs module, three TI DualCoolTM N-channel NexFET Power MOSFETs (25 V breakdown voltage) in series are assembled using flip-chip direct-bond technology. Three samples are assembled and the breakdown voltages are measured by using high-power curve tracer as 76 V, 82 V, and 72 V. The more accurate method for testing breakdown voltages by digital voltmeter obtains 77.51 V, 82.31 V, and 73.06 V. The series-connected power MOSFETs module shows compact volume, low parasitic impedances, thermal resistances and improved breakdown voltage. This power module has strong potential for use in applications that require minimized packaging size and parasitic inductance for high voltage, high switching frequency, and high efficiency. / Master of Science

This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

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En aquesta tesi hem desenvolupat models compactes que incorporen un model de transport hidrodinàmic adaptat a multi-gate (principalment double-gate (DG) and surrounding-gate (SRG) MOSFETs a partir de models unificats de control de càrrega I del potencial de superfície, obtinguts de l’equació de Poisson. Tots aquests dispositius es modelitzen seguint un esquema semblant. El corrent i càrregues totals s’escriuen en funció de les densitats de càrrega mòbil per unitat d’àrea als extrems drenador i font del canal. Els efectes de canal curt i quàntics també s’inclouen en el model compacte desenvolupat. El model desenvolupat mostra un bon acord amb simulacions numèriques 2D i 3D en tots els règims d’operació. El model desenvolupat s’implementa i testeja al simulador de circuits SMASH per a l’anàlisi dels comportaments DC i transitori de circuits CMOS. / En esta tesis hemos desarrollado modelos compactos que incorporan un modelo de transporte hidrodinámico adaptado a multi-gate (principalmente double-gate (DG) and surrounding-gate (SRG) MOSFETs a partir de modelos unificados de control de carga I del potencial de superficie, obtenidos de la ecuación de Poisson. Todos estos dispositivos se modelizan siguiendo un esquema similar. La corriente y cargas totales escriben en función de las densidades de carga móvil por unidad de área en los extremos drenador y fuente del canal. Los efectos de canal corto y cuánticos también se incluyen en el modelo compacto desarrollado. El modelo desarrollado muestra un buen acuerdo con simulaciones numéricas 2D y 3D en todos los regímenes de operación. El modelo desarrollado se implementa y testea el simulador de circuitos SMASH para el análisis de los comportamientos DC y transitorio de circuitos CMOS.

The scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x]­ core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices. / text