This thesis studies the options of using PCB embedding bare die power MOSFET and new packaging of MOSFET to increase the power density in a PCB. This is to decrease the winding losses in an isolated DC/DC converter which, according to "Flex Power Modules", can be done by improving the interleaving between the layers of the transformer and/or decreasing the AC loop. To test the MOSFET packaging two layout are made from a reference PCB, one using embedded MOSFET and the other using the new packaging. The leakage induction and winding losses are simulated and if they are lower compared to the reference PCB prototypes are manufactured. The simulated result is that PCB embedded MOSFET decrease the leakage induction but the winding loss is higher. With the new packaging the leakage induction is higher and the winding loss has linear characteristics. Only the PCB with the new MOSFET packaging is made because the MOSFET die gate pad is too small for the PCB manufacturer to make a via connection to it. The PCB is tested that it operates as a DC/DC converter with a 40-60 V input and a 12 V output. The PCB is put on a test board in a wind-tunnel to test its characteristics under different wind speeds, input voltage and loads. The result is that the PCB has a higher efficiency than the reference PCB but it has worse thermal resistance. Further development of the design needs to be made to improve the thermal resistance. Using new packaging is a way to continue the development of power converter with lower efficiency but embedding MOSFET needs a less complicated manufacturing process before there is any widespread usage.

No description available.

No description available.

The emergence of silicon-carbide (SiC) devices has been a 'game changer' in the field of power electronics. With desirable material properties such as low-loss characteristics, high blocking voltage, and high junction temperature operation, they are expected to drastically increase the power density of power electronics systems. Recent state-of-the-art designs show the power density over 17 ; however, certain factors limit the power density to increase beyond this limit. In this dissertation, three key factors are selected to increase the power density of SiC-based grid-connected three-phase converters. Throughout this dissertation, the techniques and strategies to increase the power density of SiC three-phase converters were investigated. Firstly, a magnetic integration method was introduced for the coupled inductors in the interleaved three-phase converters. Due to limited current-capacity compared to the silicon insulated-gate bipolar transistors (Si-IGBTs), discrete SiC devices or SiC modules, operate in parallel to handle a large current. When three-phase inverters are paralleled, interleaving can be used, and coupled inductors are employed to limit the circulating current. In Chapter 2, the conventional integration method was extended to integrate three coupled inductors into two; one for differential-mode circulating current and the other for common-mode circulating current. By comparing with prior research work, a 20% reduction in size and weight is demonstrated. From Chapter 3 to Chapter 5, a full-SiC uninterruptible power supply (UPS) was investigated. With the high switching frequency and fast switching dynamics of SiC devices, strategies on electromagnetic inference become more important, compared to Si-IGBT based inverters. Chapter 3 focuses on a common-mode equivalent circuit model for a topology and pulse width modulation (PWM) scheme selection, to set a noise mitigation strategy in the design phase. A three terminal common-mode electromagnetic interference (EMI) model is proposed, which predicts the impact of the dc-dc stage and a large battery-rack on the output CM noise. Based on the model, severe deterioration of noise by the dc-dc stage and battery-rack can be predicted. Special attention was paid on the selection of the dc-dc stage's topology and the PWM scheme to minimize the impact. With the mitigation strategy, a maximum 16 dB reduction on CM EMI can be achieved for a wide frequency range. In Chapter 4, an active PWM scheme for a full-SiC three-level back-to-back converter was proposed. The PWM scheme targets the size reduction of two key components: dc-link capacitors and a common-mode EMI filter. The increase in switching frequency calls for a large common-mode EMI filter, and dc-link capacitors in the three-level topology may take a considerable portion in the total volume. To reduce the common-mode noise emission, different combinations of the voltage vectors are investigated to generate center-aligned single pulse common-mode voltage. By such an alignment of common-mode voltage with different vector combinations, noise cancellation between the rectifier and the inverter can be maximally utilized, while the balancing of neutral point voltage can be achieved by the transition between the combinations. Also, to reduce the size of the dc-link capacitor for the three-level back-to-back converter, a compensation algorithm for neutral point voltage unbalance was developed for both differential-mode voltage and the common-mode voltage of the ac-ac stage. The experimental results show a 4 dB reduction on CM EMI, which leads to a 30% reduction on the required CM inductance value. When a 10% variation of neutral point voltage can be handled, the dc-link capacitance can be reduced by 56%. In Chapter 5, a 20 kW full-SiC UPS prototype was built to demonstrate a possible size-reduction with the proposed PWM scheme, as well as a selection of topologies and PWM schemes based on the model. The power density and efficiency are compared with the state-of-the-art Si-IGBT based UPSs. Chapter 6 seeks to improve power density by a change in a modulation method. Triangular conduction mode (TCM) operation of the three-level full-SiC inverter was investigated. The switching loss of SiC devices is reported to be concentrated on the turn-on instant. With zero-voltage turn-on of all switches, the switching frequency of a three-level three-phase SiC inverter can be drastically increased, compared to the hard-switching operation. This contributes to the size-reduction of the filter inductors and EMI filters. Based on the design to achieve a 99% peak efficiency, a comparison was made with a full-SiC three-level inverter, operating in continuous conduction mode (CCM), to verify the benefit of the soft switching scheme on the power density. A design procedure for an LCL filter of paralleled TCM inverters was developed. With 3.5 times high switching frequency, the total weight of the filter stage of the TCM inverter can be reduced by 15%, compared to that of the CCM inverter. Throughout this dissertation, techniques for size reduction of key components are introduced, including coupled inductors in parallel inverters, an EMI filter, dc-link capacitors, and the main boost inductor. From Chapter 2 to 5, the physical size or required value of these key components could be reduced by 20% to 56% by different schemes such as magnetic integration, EMI mitigation strategy through modeling, and an active PWM scheme. An optimization result for a full-SiC UPS showed a 40% decrease in the total volume, compared to the state-of-the-art Si-IGBT solution. Soft-switching modulation for SiC-based three-phase inverters can bring a significant increase in the switching frequency and has the potential to enhance power-density notably. A three-level three-phase full-SiC 40 kW PV inverter with TCM operation contributed to a 15% reduction on the filter weight. / Doctor of Philosophy / The power density of a power electronics system is regarded as an indicator of technological advances. The higher the power density of the power supply, the more power it can generate with the given volume and weight. The size requirement on power electronics has been driven towards tighter limits, as the dependency on electric energy increases with the electrification of transportation and the emergence of grid-connected renewable energy sources. However, the efficiency of a power electronics system is an essential factor and is regarded as a trade-off with the power density. The size of power electronics systems is largely impacted by its magnetic components for filtering, as well as its cooling system, such as a heatsink. Once the switching frequency of power semiconductors is increased to lower the burden on filtering, more loss is generated from filters and semiconductors, thus enlarging the size of the cooling system. Therefore, considering the efficiency has to be maintained at a reasonable value, the power density of Si-based converters appears to be saturated. With the emergence of wide-bandgap devices such as silicon carbide (SiC) or gallium nitride (GaN), the switching frequency of power devices can be significantly increased. This is a result of superior material properties, compared to Si-based power semiconductors. For grid-connected applications, SiC devices are adopted, due to the limitations of voltage ratings in GaN devices. Before commercial SiC devices were available, the power density of SiC- based three-phase inverters was expected to go over 20 𝑘𝑊 𝑑𝑚3 ⁄ . However, the state-of-the art designs shows the power density around 3 ~ 4 𝑘𝑊 𝑑𝑚3 ⁄ , and at most 17 𝑘𝑊 𝑑𝑚3 ⁄ . The SiC devices could increase the power density, but they have not reached the level expected. The adoption of SiC devices with faster switching was not a panacea for power density improvement. This dissertation starts with an analysis of the factors that prevent power density improvement of SiC-based, grid-connected, three-phase inverters. Three factors were identified: a limited increase in the switching frequency, large high-frequency noise generation to be filtered, and smaller but still significant magnetic components. Using a generic design procedure for three-phase inverters, each chapter seeks to frame a strategy and develop techniques to enhance the power density. For smaller magnetic components, a magnetic integration scheme is proposed for paralleled ac-dc converters. To reduce the size of the noise filter, an accurate modeling approach was taken to predict the noise phenomena during the design phase. Also, a modulation scheme to minimize the noise generation of the ac-ac stage is proposed. The validity of the proposed technique was verified by a full-SiC three-phase uninterruptible power supply with optimized hardware design. Lastly, the benefit of soft-switching modulation, which leads to a significant increase in switching frequency, was analyzed. The hardware optimization procedure was developed and compared to hard-switched three-phase inverters.

Le nitrure de gallium (GaN) est un matériau semi-conducteur de la famille III-V à large bande interdite directe, ayant des propriétés électriques et thermiques intéressantes. Grâce à sa large bande interdite, son fort champ de claquage et sa forte vitesse de saturation, il est très convoité pour la réalisation de dispositifs électroniques de puissance et de hautes fréquences pouvant fonctionner à haute température. De plus, grâce au caractère direct de sa bande interdite et son pouvoir d’émission à faible longueur d’onde, il est aussi avantageux pour la réalisation de dispositifs optoélectroniques de hautes performances en émission ou en détection tels que les DELs, les lasers ou les photo-détecteurs. Les difficultés de son élaboration, les problèmes d’inefficacités du dopage p et les densités élevées de défauts cristallins dans les couches épitaxiées ont constitué pendant longtemps des handicaps majeurs au développement des technologies GaN. Il a fallu attendre le début des années 1990 pour voir apparaître des couches épitaxiales de meilleures qualités et surtout pour obtenir un dopage p plus efficace [I. Akasaki, 2002]. Cet événement a été l’une des étapes clés qui a révolutionnée cette technologie et a permis d’amorcer son intégration dans le milieu industriel. Malgré l’avancé rapide qu’a connu le GaN et son potentiel pour la réalisation de sources optoélectroniques de haute efficacité, certains aspects de ce matériau restent encore mal maîtrisés, tels que la réalisation de contacts ohmiques avec une faible résistivité, ou encore le contrôle des interfaces métal/GaN et isolant/GaN. Les hétérostructures isolant/GaN sont généralement caractérisées par la présence d’une forte densité d’états de surface (D[indice inférieur it]). Cette forte D[indice inférieur it], aussi rapportée sur GaAs et sur d’autres matériaux III-V, détériore considérablement les performances des dispositifs réalisés et peut induire l’ancrage (‘pinning’) du niveau de Fermi. Elle constitue l’un des freins majeurs au développement d’une technologie MIS-GaN fiable et performante. Le but principal de ce projet de recherche est l’élaboration et l’optimisation d’un procédé de passivation du GaN afin de neutraliser ou minimiser l’effet de ses pièges. Les conditions de préparation de la surface du GaN avant le dépôt de la couche isolante (prétraitement chimique, gravure, prétraitement plasma etc.), les paramètres de dépôt de la couche diélectrique par PECVD (pression, température, flux de gaz, etc.) et le traitement post dépôt (tel que le recuit thermique) sont des étapes clés à investiguer pour la mise au point d’un procédé de passivation de surface efficace et pour la réalisation d’une interface isolant/GaN de bonne qualité (faible densité d’états de surface, faible densité de charges fixes, bonne modulation du potentiel de surface, etc.). Ceci permettra de lever l’un des verrous majeurs au développement de la technologie MIS-GaN et d’améliorer les performances des dispositifs micro- et optoélectroniques à base de ce matériau. Le but ultime de ce projet est la réalisation de transistors MISFETs ou MIS-HEMTs de hautes performances sur GaN.

Wide-bandgap (WBG) semiconductor materials such as silicon carbide (SiC) and gallium-nitride (GaN) allow higher voltage ratings, lower on-state voltage drops, higher switching frequencies, and higher maximum temperatures. All these advantages make them an attractive choice when high-power density and high-efficiency converters are targeted. Two different gate-driver designs for SiC power devices are presented. First, a dual-function gate-driver for a power module populated with SiC junction field-effect transistors that finds a trade-off between fast switching speeds and a low oscillative performance has been presented and experimentally verified. Second, a gate-driver for SiC metal-oxide semiconductor field-effect transistors with a short-circuit protection scheme that is able to protect the converter against short-circuit conditions without compromising the switching performance during normal operation is presented and experimentally validated. The benefits and issues of using parallel-connection as the design strategy for high-efficiency and high-power converters have been presented. In order to evaluate parallel connection, a 312 kVA three-phase SiC inverter with an efficiency of 99.3 % has been designed, built, and experimentally verified. If parallel connection is chosen as design direction, an undesired trade-off between reliability and efficiency is introduced. A reliability analysis has been performed, which has shown that the gate-source voltage stress determines the reliability of the entire system. Decreasing the positive gate-source voltage could increase the reliability without significantly affecting the efficiency. If high-temperature applications are considered, relatively little attention has been paid to passive components for harsh environments. This thesis also addresses high-temperature operation. The high-temperature performance of two different designs of inductors have been tested up to 600_C. Finally, a GaN power field-effect transistor was characterized down to cryogenic temperatures. An 85 % reduction of the on-state resistance was measured at −195_C. Finally, an experimental evaluation of a 1 kW singlephase inverter at low temperatures was performed. A 33 % reduction in losses compared to room temperature was achieved at rated power. / <p>QC 20160922</p>

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

La qualité du transport électronique est l’une des clés permettant de soutenir la progression des performances pour les futures générations de composants. De très nombreux facteurs, comme le choix de l’isolant et du métal de grille, le matériau de canal ou la présence de contraintes mécaniques, affectent de façon négative ou positive ces propriétés de transport. L’épaisseur du canal, qui atteint des dimensions nanométriques joue également un rôle : interactions avec les interfaces, fluctuations d’épaisseurs, effets de couplage électrostatique ou quantique entre ces interfaces. Il est probable que des mécanismes d’interaction associés à la proximité des zones surdopées de source et de drain puissent également intervenir. A ces dimensions, on s’attend à observer des phénomènes de transport hors d’équilibre, voire balistique, qui peuvent remettre en question la validité des paramètres utilisés pour caractériser le transport. Donc avec l'avancement de la technologie, il devient nécessaire de faire évoluer les modèles de transport et les paramètres afin de mieux expliquer le fonctionnement du MOSFET. Cette thèse se concentre sur la compréhension des modèles de transport existants et des méthodes d'extraction pour les noeuds technologiques actuels et futures. Les modèles de transport et les méthodes d'extraction de paramètres en régime linéaire et de saturation ont été explorés au cours de cette thèse. L'impact de la résistance série, qui est une fonction de la tension de grille, dans les MOSFET avancés est pris en compte et une nouvelle méthode d'extraction améliorée a été développée dans le régime linéaire. Des mesures à basse température ont été utilisées en régime linéaire pour l'extraction des mécanismes de diffusion en utilisant le modèle de mobilité. Une nouvelle méthode de correction pour le courant de drain dans le régime de saturation pour les MOSFET canal court est développée en utilisant les mesures à basse température. Cela permet de corriger du DIBL ainsi que des effets de « self heating ». Le modèle de saturation de vitesse et la méthode d'extraction associée sont explorés dans le régime de saturation et sont étudiés en fonction de la température et de la longueur de canal. Les modèles balistique et quasi-balistique avec le concept de la « kT layer » en régime de saturation sont également étudiés pour les noeuds sub 32 nm. Mesurer la magnétorésistance offre des perspectives prometteuses pour les dispositifs à canal court et permettant d’extraire directement la mobilité, sans la nécessité de la connaissance des dimensions du canal. Un modèle analytique pour la magnétorésistance est développé dans le cadre des noeuds technologiques sub 32 nm pour les modèles de transport balistique et quasi-balistique. La mesure de la magnétorésistance est explorée dans la région de saturation pour la première fois jusqu'à 50 nm sur les MOSFET « bulk » afin de comprendre l'applicabilité de cette méthode d'extraction à ce régime. Enfin les dispositifs bulk+ FDSON, FinFET, et GAA sont caractérisés en fonction de la température et les mécanismes de transport dans ces nouveaux dispositifs sont étudiés jusqu'à 35 nm (FinFET). En outre, le paramètre de champ effectif η est extrait pour les dispositifs sSOI. On trouve qu’il est différent du cas « bulk » comme c'était le cas pour les résultats obtenues sur bulk contraint et FDSOI. Cela est interprété par la rugosité de surface et la diffusion des phonons en raison de l'occupation préférentielle de la sous la bande fondamentale dans ces dispositifs avancés. / Electron transport is one of the key properties that need to be improved in order to sustain performance improvement for the next technological nodes. Many factors, such as the choice of gate stack materials, channel material or the presence of mechanical strain contribute to degrade or improve transport properties. Body thickness, which reaches dimensions of a few nanometers, is playing a role as well, through interface scattering, thickness fluctuations or electrostatic and quantum coupling effects between front and back interfaces. In addition, it is strongly suspected that additional scattering mechanisms are associated with the proximity of the highly doped source and drain regions. For the sake of sub 32nm technology nodes development, it is of fundamental importance that these various mechanisms be identified and studied. In this range of dimensions, electron transport is governed by out of equilibrium, or even ballistic, phenomena. Therefore along with the advancement in the technology nodes, it becomes necessary to evolve the transport models and parameters to better explain the MOSFET operation. This thesis focuses on understanding the existing transport models and extraction methods and improving the same under the context of current and future technology nodes mainly sub 32nm. The MOSFET transport models and static parameter extraction methods in linear and saturation regime have been explored during the course of this thesis. The impact of gate voltage dependent series resistance in the advanced MOSFETs is taken into account and a new improved extraction method has being developed in the linear regime. Low temperature measurement is used in linear regime for the extraction of scattering mechanisms using mobility model. A new saturation drain current correction for short channel MOSFETs is developed for taking into account both DIBL and self-heating using low temperature measurement. Velocity saturation vsats model and extraction method is explored in the saturation regime and vsats is studied against temperature and channel lengths. Ballistic and quasi ballistic model with concept of kT layer in saturation regime is also studied for the sake of sub 32nm nodes. Channel magnetoresistance measurement offers promising prospects for short channel devices as we can directly extract the channel mobility without the need for the knowledge of channel dimensions. An analytical magnetoresistance model is developed in the context of sub 32nm technology nodes for full ballistic and quasi ballistic transport models. Magnetoresistance measurement is explored in the saturation region for the first time down to 50nm on bulk MOSFETs in order to understand the applicability of this extraction method in this regime. Finally Bulk+ FDSON, FinFET, and GAA devices are characterized with temperature and studied the transport mechanism in these novel devices down to 35nm (FinFET). Also effective field parameter η is extracted for sSOI devices and found that this is significantly different from bulk value as in the case of previous results in strained bulk and FDSOI devices and this is interpreted as increased surface roughness and phonon scattering due to preferential sub band occupation in these advanced devices.

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.