Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck; we must find another way to improve the performance of transistor. In this study, we fully discuss the electrical characteristics and the low temperature effect as the channel of the N-MOSFET being strained. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uni-axial tensile stress. Therefore, we had improved successfully drain current and carrier mobility of NMOS, and the increasing rates are 9% and 12% respectively. In addition, we can understand the influence of low temperature effect on strain silicon by bending silicon substrate with external mechanical stress. It is great that there is no general normal single crystalline silicon to come instead in the change to temperature of Mobility and operate-current. This is this experiment was worth probing into.

Semiconductor technology has already got into nanometer scale. As the dimension keeping scaling down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find another way to improve the performance of transistor. The reliability is more important in the shorter and shorter device channel. In this study, we fully discuss the electrical characteristics of the hot carrier effect at various temperature of 65nm MOSFETs under external mechanical stress. In order to strain the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will be strained after applying uniaxial tensile stress. Therefore, we successfully improve drain current and carrier mobility of NMOS, but the hot carrier effect is more serious. In addition, we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress. With the increase of curvature, substrate current goes up. We offer an explanation to verify this result. The temperature effect is also measured. The drain current and mobility increased with the temperature decreasing, but the substrate current increased with temperature increasing.

Many trends in the silicon industry could be interpreted as the herald of the end of traditional Si scaling. If this premise holds, future performance and system-on-chip applications may not be reached with conventional Si technology extensions. We review progress towards our vision that a larger crystal structure on Si, namely relaxed SiGe epitaxial layers, can support many generations of higher performance Si CMOS and new system-on-chip functionality without the expense of significant new equipment and change to CMOS manufacturing ideology. We will review the impact of tensile strained Si layers grown on relaxed SiGe layers. Both NMOS and PMOS exhibit higher carrier mobilities due to the strained Si MOSFET channel. Heterostructure MOSFETs designed on relaxed SiGe can have multiple-generation performance increases, and therefore determine a new performance roadmap for Si CMOS technology, independent of MOSFET gate length. We also indicate that this materials platform naturally leads to incorporating new optical functionality into Si CMOS technology. / Singapore-MIT Alliance (SMA)

We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si₀.₃Ge₀.₇ virtual substrates. The poor interface between silicon dioxide (SiO₂) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400° C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly 8 times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm²/V-s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement mode MOSFET with buried channel-like transport characteristics. / Singapore-MIT Alliance (SMA)

Two SiGe-on-insulator (SGOI) structures for CMOS application are presented: surface-channel strained-Si on SGOI (SSOI) and dual-channel SGOI structures. Comparisons between two structures are made from both device performance and CMOS process point of view. We have demonstrated both structures on SGOI, and have fabricated n-MOSFET’s and p-MOSFET’s on those two structures respectively. Device characteristics are presented. The devices show enhancement on both electron and hole mobilities. / Singapore-MIT Alliance (SMA)

PMOS and NMOS mobility characteristics of the dual channel (strained Si/strained Ge) heterostructure have been reviewed. It is shown that the dual channel heterostructure can provide substantially enhanced mobilities for both electrons and holes. However, germanium interdiffusion from the germanium rich buried layer into the underlying buffer layer could potentially reduce the hole mobility enhancements. / Singapore-MIT Alliance (SMA)

In this work, we have developed two different fabrication processes for relaxed Si₁₋xGex-on-insulator (SGOI) substrates: (1) SGOI fabrication by etch-back approach, and (2) by "smart-cut" approach utilizing hydrogen implantation. Etch-back approach produces SGOI substrate with less defects in SiGe film, but the SiGe film uniformity is inferior. "Smart-cut" approach has better control on the SiGe film thickness and uniformity, and is applicable to wider Ge content range of the SiGe film. We have also fabricated strained-Si n-MOSFET’s on SGOI substrates, in which epitaxial regrowth was used to produce the surface strained Si layer on relaxed SGOI substrate, followed by large-area n-MOSFET’s fabrication on this structure. The measured electron mobility shows significant enhancement (1.7 times) over both the universal mobility and that of co-processed bulk-Si MOSFET’s. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si₁₋xGex layer. / Singapore-MIT Alliance (SMA)