• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 66
  • 12
  • Tagged with
  • 78
  • 78
  • 77
  • 37
  • 20
  • 15
  • 14
  • 14
  • 14
  • 13
  • 11
  • 11
  • 11
  • 7
  • 6
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
61

A 33 µW Sub-3 dB Noise Figure Low Noise Amplifier for Medical Ultrasound Applications

Hansen, Hans Herman January 2011 (has links)
The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total noise of the receiversystem will be dominated by that of the amplifier. For most low noise amplifier,there is a fundamental trade–off between accuracy and power consumption, whichmakes it difficult to design micro power front–end amplifiers with excellent noiseperformance. In some cases, however, lower accuracy can be tolerated if the sourceitself is noisy. This is the case for small, high impedance sources, where the noiselevel is in the region of 18 nV/sqrt{Hz}.This thesis presents the design and simulations of a low noise amplifier instandard 180 nm CMOS suitable for use with high impedance sources. In fact,high impedance sources pose challenges on the biasing of voltage amplifiers,where maintaining high input impedance is necessary. In addition, for differentialamplifiers, implementing common–mode feedback will typically result in a significantincrease in power consumption and area overhead. To alleviate this problem, aswitched common–mode feedback scheme is implemented, that also provide highinput impedance biasing of the input transistors.In order to cope with the large dynamic range requirement inherent in manyultrasound modalities, variable gain is often used to compress the dynamic rangefor the analog front–end. Methods for adding variable gain without resulting in alarge increase in area and power consumption is therefore of huge interest in manyultrasound applications. Several methods of adding variable gain is investigated inthis thesis, and a capacitive attenuator is proposed, which causes minimum increasein noise factor, while increasing the gain range by at least 20 dB.Large scale integration of several thousands analog front–ends in a singleultrasound probe handle requires low power consumption and minimum areaoverhead for all parts of the analog front–end, including the low noise amplifier.By using a figure–of–merit based optimization technique, the designed amplifiertopology achieves an low power consumption of 17.3 μA, while maintaining a noisefactor of less than 3 dB at resonance. In addition to performing a single–ended todifferential conversion, this amplifier realizes a maximum voltage gain of 23.4 dB,with a 3 dB bandwidth of 21.5 MHz.
62

A sub-1µW, 16kHz Current-Mode SAR-ADC for Neural Spike Recording

Haaheim, Bård January 2011 (has links)
This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh power efficiency and is designed to operate at a 1.8V supply. The ADC isrunning at a 16kHz sampling frequency using under 1uW of power, thoughis adjustable using the featured calibration registers. A finished layout ispresented, occupying less than 0.078mm2. Linear operation through mismatchand process variations is obtained using a current calibration circuitconnected to both the current mode DAC and all the biases. This ensuresINL < 0.5 and DNL < 1, yielding no missing codes and a 3sigma productionyield. Calibration is needed because of the relatively large mismatch causedby sub-threshold operation of the current mirrors. The design also offers anewly developed current comparator with high resolution and fast settlingrelative to the current level and is completable with other state-of-the-art solutions,though still feature some voltage scaling issues left for future work.
63

HDMI Transmitter

Nystøyl, Bjarte Løken January 2012 (has links)
HDMI is the de facto global standard for connecting HD components and bridging the gap between consumer electronics and personal computer products, making it a priority to develop efficient hand-held, battery-powered units that support the standard.This is a study into how to design a low power and high performance system that can transmit HDMI-signals to a valid HDMI-receiver. The main priority is to implement the TMDS part of a HDMI-transmitter, where parallel data is encoded and serialized at high frequencies. The theory chapters provides an orderly summary of the complex workings of the HDMI-standard, in addition to an introduction to high-performance digital circuit design. This is followed by a system specification chapter, which sets the constraints of the design and discusses the hardware requirements. The subsequent chapter first deals with the design of a straightforward, basic HDMI-transmitter, before moving on to an enhanced design process. The basic design is used as a base for discussions in regard to how effective the suggested enhancement techniques are. The improvements result in an enhanced design able to operate at 742,5 MHz and support High-Definition video at the impressive resolution of 1080p30. This is achieved by using a 180nm, low-leakage library, and the final design consists of approximately 24.000 unit-sized transistor equivalents, consuming approximately a total of 13,6 mW.
64

Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS

Steen-Hansen, Eirik January 2012 (has links)
A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. Thefirst stage is a modified pipelined ADC stage, while the other stages uses aninterpolator to resolve the signals, the focus is on designing these stages. Thedual-residue architecture is insensitive to the gain of the residue amplifiers, andonly a matching between two amplifiers is necessary. Limiting parameters of theADC is the offset in the residue amplifiers, as well as gain mismatch betweenthe amplifiers. The maximum allowed offset voltage of the residue amplifier isVlsb/2 , and maximum allowable mismatch between the two residue amplifiers is 1/256 for a 9-bit ADC. Multiple amplifier topologies were discussed and the bestcandidate for residue amplification is found to be a zero-crossing based amplifier.With this type of amplifier the last 8 stages of the ADC has an estimated powerconsumption of 2.1mW.
65

Electrical Power System of the NTNU Test Satellite : Design of the EPS

Jacobsen, Lars Erik January 2012 (has links)
The NTNU Test Satellite (NUTS) project is aiming to launch a 10×10×20 cm nanosatellite by the year 2014. The goal is to design and develope a low cost satellite by exploring the use of commersially available components. This work will focus on the power system of the NUTS satellite, which consists of a power distribution system, the backplane, and a power condition system, the Electrical Power System (EPS).This thesis describes the design and evaluation of the EPS module, which is a critical part of the satellite, because without power the satellite will not be able to operate. The electrical power system of the satellite consists of the solar cells, batteries, and voltage converters. With limited power available, the main focus of the design has been to implement an efficient system with minimum losses in power conversions.The Electrical Power System (EPS) module has been designed with simplicity, reliability, and redundancy in mind. The designed is based on the requirements of a reliable power source, with the main goals of charging the batteries with power from the solar cells and regulate the battery voltage down to the requested voltages of the backplane. A charger is chosen for its abilities to provide efficient and safe charging by using proper strategies for efficient energy harvesting and charging. To accommodate the voltage request of the backplane, four fixed value regulators is chosen for the design. For power monitoring of the provided power from the solar cells and batteries, current monitor sensors are implemented after each charger circuit and the batteries. Based on the specification of the solar cells and the batteries a final design of the main functionalities has been provided and a prototype of the EPS module has been produced.The proposed solution offers a reliable and redundant system, where a loss of one charger or converter will not mean the end of the mission. The EPS module has been tested and evaluated, and displays good performance results in terms of charging the batteries and voltage regulation. The efficiency of the EPS chargers is found to be 95 %.
66

Integration of a Fractal Generator with Mali GPU

Kjøll, Per Kristian January 2012 (has links)
The Mandelbrot set is a well-known fractal with mathematical propertiesthat can be exploited to create 3D-landscapes. The operations required tocalculate a heightmap using the Mandelbrot set are highly parallelizableand is thus suitable for a hardware implementation. Generation of 3D-landscapes,on-the-y, using the Mandelbrot set is desirable since the Mandel-brot set is innitely complex[4] and deterministic. This makes possible thecreation of many dierent landscapes with complex patters in, for example,computer games.A previous master thesis[4] presents a vertex array generator(VAG) thatgenerates the vertices of a 3D-landscape based on an area of the Mandelbrotset. This thesis explores dierent architectures that connect this vertex arraygenerator with the Mali-400 graphics processing unit(GPU). The result isthat the VAG in its current state is not suitable for integration, mostly sinceit does not support random access to vertices. Thus, a new fractal generatorarchitecture is presented, reusing parts of the VAG.The new fractal generator is implemented in Verilog and its functionalityis veried using the Universal Verication Methodology(UVM). Then, thefractal generator is integrated with the Mali-400 GPU in an FPGA frame-work and synthesized on FPGA. Tests are also performed at each step ofintegration.An OpenGL for Embedded Systems 2.0 demo is written to showcase thefunctionality of the fractal generator. Changes have been made to the Mali-400 drivers to automatically congure and set-up the fractal generator whilethe demo is running.The fractal generator is shown to be working as intended with a scalableperformance based on a number of internal cores. Using 64 cores the fractalgenerator has a worst-case frame time of 51.1 ms at 400Mhz which equals aframe rate of 450 frames pr second, vastly outperforming a software imple-mentation.The fractal generator is currently limited to creating landscapes of 128x128points, the intention was to use the demo and driver to increase the resolutionbut this has not been solved.Increasing the resolution and optimizing the cache size of the fractal generatorhas been left for future work.
67

Current-Mode SAR-ADC In 180nm CMOS Technology

Eilertsen, Bård Egil January 2012 (has links)
This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.
68

Kalman Smoothing Techniques in Medical Image Segmentation

Storve, Sigurd January 2012 (has links)
An existing C++ library for efficient segmentation of ultrasound recordings by means of Kalman filtering, the real-time contour tracking library (RCTL), is used as a building block to implement and assess the performance of different Kalman smoothing techniques: fixed-point, fixed-lag, and fixed-interval smoothing. An experimental smoothing technique based on fusion of tracking results and learned mean state estimates at different positions in the heart-cycle is proposed. A set of $29$ recordings with ground-truth left ventricle segmentations provided by a trained medical doctor is used for the performance evaluation.The clinical motivation is to improve the accuracy of automatic left-ventricle tracking, which can be applied to improve the automatic measurement of clinically important parameters such as the ejection fraction. The evaluation shows that none of the smoothing techniques offer significant improvements over regular Kalman filtering. For the Kalman smoothing algorithms, it is argued to be a consequence of the way edge-detection measurements are performed internally in the library. The statistical smoother's lack of improvement is explained by too large interpersonal variations; the mean left-ventricular deformation pattern does not generalize well to individual cases.
69

Ambient-light Photoplethysmography : - How can I tell your pulse from looking at your face?

Rustand, Åsmund January 2012 (has links)
This thesis is an attempt to explore certain aspects of the subject called non-contact, ambient-light photoplethysmography, where we hope to reveal benecialproperties the technique may have. We have a clear focus on technical possibilitybut the medical relevance of it is also discussed and conrmed.Conclusions from previous work are exemplied { the ability we have with thismethod to compute an exact heart rate estimate, from the skin surface both onour face and in the palm of our hand, with and without the subject moving duringrecording; the presence of signal uctuations akin to those of breathing. Moreover,that the pulsations are strong enough to enable subdivision into smaller segmentsand a mapping of how the pulse amplitude is distributed among them.Other information is obtained: the phase information contained in the signalis robust enough that not only the average heart rate over some time but also itsshort time variability can be seen with more than a minimum of detail resolution.From a recording where both face and hand is in view, we further substantiate theclaim of phase robustness by estimating the phase delay, i.e. the dierence in bloodpressure wave travel time between forehead and palm.The concept of Independent Component Analysis has been suggested as a way ofimproving the output of the method|a procedure we investigate and nd limitedsupport for. Other, more simplistic signal processing approaches are found to havepositive traits in achieving overall signal clarity.
70

3D-overflatemodellering basert på stereoskopiske bilder / 3D Surface Modeling based on Stereoscopic Images

Røren, Thomas Thorsen January 2012 (has links)
Prosjektet har omhandlet utvikling av en prototype 3D-modell som er basert på stereoskopiske bilder. Hensikten er å modellere kroniske hudsår for visualisering og dybdeestimering av sårene. Modelleringen vil kunne brukes til areal- og volumberegninger av sårene som gir verdifull diagnostisk informasjon. Det ble gjort geometrisk kalibrering, bilderektifikasjon og bildematching av stereobildene for å kunne foreta modelleringen. Utfordringer under disse prosessene var knyttet til presisjon av bildematchingen av homogene områder og høydeoppløsningen i modellen. Bildematchingen kan forbedres ved å forbehandle stereobildene for å øke kontrasten, og høydeoppløsningen kan økes ved å endre det eksperimentelle oppsettet. Som en videreføring av dette prosjektet skal 3D-modelleringen kombineres med hyperspektrale avbildninger for i tillegg å kunne gi spektral informasjon om såret.

Page generated in 0.0741 seconds