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Orientador: Alberto Martins Jorge / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-07T17:31:45Z (GMT). No. of bitstreams: 1 Bertone_OsvaldoHugo_M.pdf: 1638189 bytes, checksum: de96158c2363994f79a61d1d7ce1e9aa (MD5) Previous issue date: 2005 / Resumo: Neste trabalho é proposto um Registrador Cíclico para circuitos MVL (Multi-valued Logic) utilizando transistores NMOS e PMOS para uma configuração de quatro níveis lógicos. Este circuito usa certas características secundárias (normalmente indesejadas) dos transistores MOS. Uma particularidade deste registrador são os níveis lógicos auto-definidos com uma alta precisão. Isto permite incrementar a Lógica para mais valores, não estando limitada somente a Lógica Ternária ou Quaternária (as mais usadas em circuitos MVLs), seu uso pode ser estendido para Decimal, Hexadecimal ou mais. O Registrador Cíclico proposto, alem de armazenar um dado multi-valor com um nível de tensão preciso, ainda, fornece a saída com qualquer possível deslocamento lógico sem degradação da precisão. Este registrador permitirá o desenvolvimento de circuitos lógicos como contadores, toggle switches, shift registers, flip-flops em vários níveis, deslocamentos de valores (negação de Post), conversores D/A e A/D, etc¿ Algumas vantagens que este circuito oferece é sua alta resposta em freqüência e sua pouca dependência dos parâmetros do transistor, alcançando uma robustez comparável com os circuitos binários. Como uma aplicação deste registrador proposto é apresentado um Multiplicador Quaternário e comparado com um Multiplicador Binário utilizando a mesma tecnologia. Neste texto serão desenvolvidos os circuitos e simulados no OrCad (PSpice [01]) utilizando um modelo de transistor NMOS e outro PMOS fornecidos pela foundry AMS (Austria Micro Systems) descritos no Apêndice I. O Registrador Cíclico para circuitos MVL foi apresentado pelo autor no Congresso SUCESU 2005 no dia 31 de março de 2005 em Belo Horizonte, MG, Brasil / Abstract: The Cyclical Register for MVL circuits (Multi-valued Logic) proposed is composed by NMOS and PMOS Transistors. This circuit uses the advantage of certain secondary characteristics (normally undesirable) of the MOS transistors. One peculiarity of this register is that the logical levels are defined by itself with a very high precision ; this, permits to increase the logic to many values. Since it is not limited to ternary or quaternary logic (more used MVLs), its use can be extended to decimal, hexadecimal and others. The proposed cyclical register, besides storing the multi-value data with precise voltage level, still, supplies the output with any possible logical shift without the degradation of precision. This register will allow the development of logical circuits as counter, toggle switch, shift register, flip-flop in several levels, shift of value, D/A and A/D converter, etc¿ Some advantages that this circuit offers is its high frequency response and its minor dependency of the parameter of the transistors, providing a robustness comparable to the current binary circuits. As an application of this proposed Register a Quaternary Multiplier is presented and compared with the Binary Multiplier with the same technology. On this paper the circuits will be developed and simulated in the OrCad (Pspice [01]), using the transistors models NMOS and PMOS supplied by foundry AMS (Austria Micro Systems) detailed in the Appendix I. The Cyclical Register for MVL circuits was presented by the author in the Congress SUCESU 2005 in March 31st, 2005 in Belo Horizonte, MG, Brazil / Mestrado / Microeletronica / Mestre em Engenharia Elétrica

This dissertation titled Teaching English to Deaf and Hard-of-hearing University Students aims to portray a picture of the situation of teaching English to university students, more specifically of those studying at Charles University in Prague. The work is divided into two main parts. The first part brings general insight, also from linguistic perspective, into language competences and language acquisition by the hearing impaired. It describes variables and possible variables affecting spoken language acquisition by this minority. It gives basic overview of different levels of hearing loss on the grouds of medicine assessment of hearing loss. The dissertiation stresses out the neccessity of educating these students with respect to linguistic research and findings. Moreover, it emphasizes the needs to interweave linguistics and pedagogy and benefits of linguistics research and methods such as error analysis and contrastive analysis for enhancement of language productive skills of hearing impaired students. The second part of the dissertation is devoted to the research of English language teaching to hearing impaired students at Charles University in Prague. The work summarizes the findings of five-year long research carried out at the Language Resource Centre, Faculty of Arts, Charles University in...

Orientador: Alberto Martins Jorge / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-09T08:44:01Z (GMT). No. of bitstreams: 1 MingotoJunior_CarlosRoberto_M.pdf: 657421 bytes, checksum: dc6ef4bc58fb70a90293781871a969c6 (MD5) Previous issue date: 2005 / Resumo: Os circuitos quaternários são uma alternativa para o processamento das informações, que, atualmente, acontece de forma binária. Ainda em fase de definições, a lógica multivalores mostra-se como um campo de pesquisas que pode auxiliar a busca pelo incremento de desempenho e redução de área de ocupação dos transistores de um circuito integrado. A lógica multi-valores utilizando-se de quatro dígitos na representação das informações é a lógica quaternária. Neste trabalho são propostos alguns blocos básicos de circuitos eletrônicos quaternários que, progressivamente, são aglutinados formando blocos mais complexos para finalmente construir-se um circuito meio-somador, um somador completo e um multiplicador quaternários. As montagens são feitas e testadas em simulador de circuitos eletrônicos e operam em modo corrente com transistores bipolares NPN e PNP / Abstract: The quaternary circuits are an alternative to data processing that, nowadays, occurs in a binary way. Still in a definition stage, the multiple-valued logic seems to be a research area to aid the increase of performance and reduction of area of the transistors inside an integrated circuit. The multiple-valued logic using four digits to represent the data is called quaternary logic. In this work are proposed some basic blocks of electronic quaternary circuit which are progressively joined to become more complex blocks and finally a half-adder, a full adder and a multiplier. The configurations are done and evaluated in a circuit simulator operating in a current-mode with bipolar NPN and PNP transistors / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.

The large amount of non-degradable plastic waste has become a significant environmental concern, leading to an increased need for degradable plastics. Here in, to create degradable polymers, polyesters were produced through radical ring opening polymerization using cyclic ketene acetals. The cyclic ketene acetal monomer 5,6-benzo-2-methylene-1,3-dioxepane has been prepared for the synthesis of homo- and copolymers with methyl methacrylate, α-methylene-γ-valerolactone, α-methylene-γ-butyrolactone, cholesterol methacrylate and limonene acrylate. The polymerization was conducted using radical ring opening polymerization both in bulk and solution polymerization. The structural characteristics of the polymer were determined by different characterization methodologies, including TGA, DSC, SEC, FTIR and 1D 1H-NMR. The results obtained from 1H-NMR analysis showed the composition of the copolymers. TGA analysis revealed the thermal stability of the polymers and their degradation patterns. DSC analysis provided information about the glass transition temperatures (Tg’s) of the polymers. Moreover, the Tg indicated the presence and amounts of comonomers in the copolymers. Overall, the results showed the influence of different comonomers on the properties of the polymers by successfully incorporating the comonomers in the polymer. The thermal properties for polymers containing methyl methacrylate became more thermally stable. The Tg, analyzed with DSC, shifted from the Tg of homopolymers indicating the incorporation of both monomers. The polymers were successfully degraded via hydrolysis in alkaline conditions breaking them down into smaller pieces making them easier to recycle. To conclude, the results all indicate that the incorporation of BMDO and thereby possibly other CKA-monomers into the polymer chains of commonly used plastics could provide valuable tools in the recycling of said plastics.