Much of today's high performance computing engines and hand-held mobile devices are products of aggressive CMOS scaling. Technology scaling in semiconductor industry is mainly driven by corresponding improvements in optical lithography technology. Photolithography, the art used to create patterns on the wafer is at the heart of the semiconductor manufacturing process. Lately, improvements in optical technology have been difficult and slow. The transition to deep ultra-violet (DUV) light source (193nm) required changes in lens materials, mask blanks, light source and photoresist. It took more than ten years to develop a stable chemically amplified resist (CAR) for DUV. Consequently, as the industry moves towards manufacturing end-of-the-roadmap CMOS devices, lithography is still based on 193nm light source to print critical dimensions of 45nm, 32nm and likely 22nm. Sub-wavelength lithography creates a number of printability issues. The printed patterns are highly sensitive to topographic changes due to metal planarization, overlay errors, focus and dose variations, random particle defects to name a few. Design for Manufacturability methodologies came into being to help analyze and mitigate manufacturing impacts on the design. Although techniques such as Resolution Enhancement Techniques (RET) which involve optical proximity correction (OPC), phase shift masking (PSM), off-axis illumination (OAI) have been used to greatly improve the printability and better the manufacturing process window, they cannot perfectly compensate for these lithographic deficiencies. DFM methods were primarily devised to predict and correct systematic patterning problems that arise during manufacturing. Apart from systematic errors, random manufacturing variations may occur during photolithography. This is where a statistical approach to modeling of error behavior and its impact on different design parameters may prove to be effective. By incorporating statistical analysis to parameter variation, an effective, non-conservative design can be obtained. IC manufacturing yield is the foremost measure that determines the profitability of a given semiconductor manufacturing process. Thus early prediction of yield detractors is an important step in the design process. Such predictions are based on models, which in turn are rooted in manufacturing process. Success of yield prediction is based on quality of models. The models must capture physical phenomena and yet be efficient for computation. In this work, we present a lithography-based yield model that is computationally practical for use in the design process. The work also provides a methodology to perform statistical lithography rules check to identify hot spots in the design that can contribute to yield loss. Yield recovery methods aimed at minimally modifying the design ultimately produce more printable masks. Apart from IC manufacturing yield, ICs today are vulnerable to various reliability failures including electromigration (EM), negative bias temperature instability (NBTI), hot carrier injection (HCI) and electro-static discharge (ESD). Though such reliability issues have been examined since the beginning of CMOS, manufacturability impacts have created a renewed interest in analyzing them. In this dissertation, we introduce the concept of Design for reliable manufacturability (DFRM) to consider the effect of linewidth changes, gate oxide thickness variations and other manufacturing artifacts. A novel Litho-aware EM calibration and analysis has bee shown in this work. Results indicate that there is a significant difference in EM estimation when litho-predicted layouts are considered during analysis. DFM has always looked at linewidth and material thickness variation as detractors to the design. However, such variations are inevitable. In this work we also consider modeling sensitivity to variations to improve test pattern quality. Test structures sprinkled all over the wafer encounter varying process fluctuations. This can be harnessed to predict the current lithographic process corner which will later be used to choose the test pattern set that results in maximum fault coverage. In summary, the objective of this dissertation is to consider the impact of sub-wavelength lithography on printability and the overall impact on circuit reliability and manufacturing test development.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

Dans un contexte industriel compétitif, une prévision fiable du rendement est une information primordiale pour déterminer avec précision les coûts de production et donc assurer la rentabilité d'un projet. La quantification des risques en amont du démarrage d'un processus de fabrication permet des prises de décision efficaces. Durant la phase de conception d'un produit, les efforts de développement peuvent être alors identifiés et ordonnés par priorité. Afin de mesurer l'impact des fluctuations des procédés industriels sur les performances d'un produit donné, la construction de la probabilité du risque défaillance est développée dans cette thèse. La relation complexe entre le processus de fabrication et le produit conçu (non linéaire, caractéristiques multi-modales...) est assurée par une méthode de régression bayésienne. Un champ aléatoire représente ainsi, pour chaque configuration du produit, l'information disponible concernant la probabilité de défaillance. Après une présentation du modèle gaussien, nous décrivons un raisonnement bayésien évitant le choix a priori des paramètres de position et d'échelle. Dans notre modèle, le mélange gaussien a priori, conditionné par des données mesurées (ou calculées), conduit à un posterior caractérisé par une distribution de Student multivariée. La nature probabiliste du modèle est alors exploitée pour construire une probabilité de risque de défaillance, définie comme une variable aléatoire. Pour ce faire, notre approche consiste à considérer comme aléatoire toutes les données inconnues, inaccessibles ou fluctuantes. Afin de propager les incertitudes, une approche basée sur les ensembles flous fournit un cadre approprié pour la mise en œuvre d'un modèle bayésien imitant le raisonnement d'expert. L'idée sous-jacente est d'ajouter un minimum d'information a priori dans le modèle du risque de défaillance. Notre méthodologie a été mise en œuvre dans un logiciel nommé GoNoGo. La pertinence de cette approche est illustrée par des exemples théoriques ainsi que sur un exemple réel provenant de la société STMicroelectronics. / In competitive industries, a reliable yield forecasting is a prime factor to accurately determine the production costs and therefore ensure profitability. Indeed, quantifying the risks long before the effective manufacturing process enables fact-based decision-making. From the development stage, improvement efforts can be early identified and prioritized. In order to measure the impact of industrial process fluctuations on the product performances, the construction of a failure risk probability estimator is developed in this thesis. The complex relationship between the process technology and the product design (non linearities, multi-modal features...) is handled via random process regression. A random field encodes, for each product configuration, the available information regarding the risk of non-compliance. After a presentation of the Gaussian model approach, we describe a Bayesian reasoning avoiding a priori choices of location and scale parameters. The Gaussian mixture prior, conditioned by measured (or calculated) data, yields a posterior characterized by a multivariate Student distribution. The probabilistic nature of the model is then operated to derive a failure risk probability, defined as a random variable. To do this, our approach is to consider as random all unknown, inaccessible or fluctuating data. In order to propagate uncertainties, a fuzzy set approach provides an appropriate framework for the implementation of a Bayesian model mimicking expert elicitation. The underlying leitmotiv is to insert minimal a priori information in the failure risk model. Our reasoning has been implemented in a software called GoNoGo. The relevancy of this concept is illustrated with theoretical examples and on real-data example coming from the company STMicroelectronics.

Inkjet printing has emerged from a digital graphic arts printing technology to become a versatile tool for the patterned deposition of functional materials. This thesis contributes to the research in the area of functional inkjet printing by focusing on two different topics: (i) inkjet printing of colloidal suspensions to study the principles of deposit formation and to develop deposits with photonic properties based on self-assembly, and (ii) the development of a reliable manufacturing process for all-inkjet-printed thin-film transistors, highlighting the importance of selection of materials and inks, print pattern generation, and the interplay between ink, substrate and printing conditions. (i) Colloidal suspensions containing nanospheres were applied as ink formulation in order to study the fundamental processes of layer formation and to develop structures with periodically arranged nanospheres allowing the modulation of electromagnetic waves. Evaporation-driven self-assembly was found to be the main driver for the formation of the final deposit morphology. Fine-tuning of inkjet process parameters allows the deposition of highly ordered structures of nanospheres to be arranged as monolayer, multilayer or even three-dimensional assemblies with a microscopic spherical shape. (ii) This thesis demonstrates the development of a manufacturing process for thin-film transistors based on inkjet printing. The knowledge obtained from the study with the colloidal nanospheres is used to generate homogeneous and continuous thin films that are stacked well-aligned to each other to form transistors. Industrial printheads were applied in the manufacturing process, allowing for the up-scaling of the manufacturing by printing of several thousands of devices, and thus the possibility to study the process yield as a function of printing parameters. The discrete droplet-by-droplet nature of the inkjet printing process imposes challenges on the control of printed patterns. Inkjet printing of electronic devices requires a detailed understanding about the process and all of the parameters that influence morphological or functional characteristics of the deposits, such as the selection of appropriate inks and materials, the orientation of the print pattern layout to the deposition process and the reliability of the inkjet process.

Inkjet printing has emerged from a digital graphic arts printing technology to become a versatile tool for the patterned deposition of functional materials. This thesis contributes to the research in the area of functional inkjet printing by focusing on two different topics: (i) inkjet printing of colloidal suspensions to study the principles of deposit formation and to develop deposits with photonic properties based on self-assembly, and (ii) the development of a reliable manufacturing process for all-inkjet-printed thin-film transistors, highlighting the importance of selection of materials and inks, print pattern generation, and the interplay between ink, substrate and printing conditions. (i) Colloidal suspensions containing nanospheres were applied as ink formulation in order to study the fundamental processes of layer formation and to develop structures with periodically arranged nanospheres allowing the modulation of electromagnetic waves. Evaporation-driven self-assembly was found to be the main driver for the formation of the final deposit morphology. Fine-tuning of inkjet process parameters allows the deposition of highly ordered structures of nanospheres to be arranged as monolayer, multilayer or even three-dimensional assemblies with a microscopic spherical shape. (ii) This thesis demonstrates the development of a manufacturing process for thin-film transistors based on inkjet printing. The knowledge obtained from the study with the colloidal nanospheres is used to generate homogeneous and continuous thin films that are stacked well-aligned to each other to form transistors. Industrial printheads were applied in the manufacturing process, allowing for the up-scaling of the manufacturing by printing of several thousands of devices, and thus the possibility to study the process yield as a function of printing parameters. The discrete droplet-by-droplet nature of the inkjet printing process imposes challenges on the control of printed patterns. Inkjet printing of electronic devices requires a detailed understanding about the process and all of the parameters that influence morphological or functional characteristics of the deposits, such as the selection of appropriate inks and materials, the orientation of the print pattern layout to the deposition process and the reliability of the inkjet process.:Bibliography II Abstract III Preface and acknowledgements IV On the major results and novelty of the thesis VII Table of contents VIII List of abbreviations and symbols X List of figures XII List of tables XX 1 Introduction 1 2 Fundamentals 6 2.1 Inkjet printing – an overview 6 2.2 Piezoelectric inkjet technology and a historical overview of inkjet printing 10 2.3 Pattern and film formation in inkjet printing under the scheme of self-assembly 20 2.4 Inkjet printing of colloidal nanospheres 27 2.5 Spherical colloidal assemblies 29 2.6 All-inkjet-printed thin film transistors 31 3 Experimental section 35 3.1 Inkjet printing systems and accessories 35 3.2 Inks and substrates 38 3.3 Print patterns 43 3.4 Post-processing 46 3.5 Optical, morphological and functional characterization 47 4 Inkjet printing of colloidal nanospheres: Evaporation-driven self-assembly based on ink-substrate interaction 49 4.1 Single droplet deposit morphology: Interaction of substrate and ink 49 4.2 Optical properties of inkjet-printed single droplet monolayers and multilayers 54 5 Inkjet printing of colloidal nanospheres: Evaporation-driven self-assembly of SCAs independent on substrate properties 58 5.1 Inkjet printing of spherical colloidal assemblies and their identification 58 5.2 Fine-tuning of the waveform applied to the printhead 60 5.3 Interaction of substrate and ink 66 5.4 Structures, morphologies and materials of SCAs 68 5.5 Optical properties of SCAs 76 6 Inkjet printing of TFTs: Process development and process reliability 80 6.1 Influence of print layout design 80 6.2 Selection of materials and inks 91 6.3 Manufacturing workflow and electrical TFT parameters 108 6.4 Manufacturing yields and failure origins 113 7 Summary and conclusion 124 References 127 Documentation of authorship and contribution of third persons 149 List of publications 151 APPENDIX A Formation of colloidal hemispheres on hydrophobic PTFE substrates 161 APPENDIX B Inkjet-printed higher-order cluster with N < 100 using BL280 162 APPENDIX C Inkjet-printed SCAs based on BS305 with similar sizes and inkjet-printed SCA based on PSC221 163 APPENDIX D Microreflectance spectra of SCAs and the processing of the spectra using the Savitzky-Golay filter with a second-order polynomial and a moving window of 100 data points 164 APPENDIX E Waveform, drop ejection and photographs of the printed patterns of Sun Chemical EMD5603 and UTDots UTDAgIJ1 165 APPENDIX F Smoothening of profiles obtained by profilometry of EMD5603 and UTDAgIJ1 and dependency of print resolution of layer height 166 APPENDIX G Percentage of area increase based on a 4 mm x 4 mm digital print pattern using the ink Harima NPS-JL and influence of print resolution and post-treatment temperature on sheets resistance 168 APPENDIX H Cross-sectional view of a TFT stack printed with the dielectric Sun Chemical EMD6415 that shows high layer thickness due to ink contraction after the deposition as presented in Figure 46 169 APPENDIX I Influence of printing parameters on the dielectric layer applied in the TFT 170 APPENDIX J Reduction of channel length by decreasing the S-D electrode channel length in the print pattern layout 171

Printing since many years has been a well-known high throughput technology for producing replications of graphic arts entities (texts, images, aesthetics, gloss and physical impressions) over large varieties of substrates which are dedicated for various needful applications like newspapers, magazines, posters, official documents, packages, braille, textiles, decorative articles and many more. Due to the fact, that printing is a liquid-solution based replication process, where basic ink and substrate are needed, it is now not only limited to printing of graphic arts. Whenever an ink is deposited over a defined substrate and the process can be multiplied, it can be termed as printing and once the final product contains a functionality other than graphic arts application, it can be called as “Printed Functionality”. Some examples for printed functionalities can be found in the following fields: A. Printed electronics (using inks having electronic properties); B. Printed micro-fluidics (using inks having polymeric and elastic properties for directive purposes); C. 3-Dimensional printing (using inks containing binding properties for developing three dimensional structures); D. Printed photonics (using inks having self-assembling properties for building-up symmetric micro-structures); E. Printed pyroelectrics (using inks containing thermally flammable properties); F. Printed ceramics (using inks with ceramic particles) and G. Printed optics and functional surfaces (using inks with transparency, absorbency and reflective properties). All these mentioned applications require functional inks which in turn exhibits some physical-chemical properties e.g. particle size, particle loading, fluid’s rheological properties etc. These properties determine the feasibility of the material’s deposition (in this case the functional inks) with a suitable printing technology. The inkjet printing technology among others has several advantages such as contactless deposition processability, digitalization (batch size one & turn-over time zero), user defined customization and adaptation, industrial relevance, minimal ink demand for R&Ds, freedom of substrate regularity and µm-scale print accuracy etc. Some of the imminent players in the inkjet printing technology market are Canon, Kodak, Hewlett Packard, Fujifilm Dimatix, Konica Minolta and XAAR. They provide print solutions from small to industrial scale printheads, printers, equipments and accessories for the realization of huge variety of application ideas. The inkjet is a versatile, but yet matured technology which finds its use in various application areas e.g. home office documentation, large format posters, variable data printing, security printing, textile printing, wallpapers, household articles, curved surfaces like bottles, printing over edible items, printing of elevated surfaces etc. And, hence there are several literatures published which show the use of the inkjet printing technology in the development of products for printed electronics. Some of the common examples are development of passive and active devices e.g. capacitors, resistors, thin-film-transistors, photovoltaics, sensors, circuits like logic gates for electronic switching, device arrays for detection purposes, point of care health applications, energy harvesting applications etc. But, the exploitation of the inkjet technology has not been intense enough to declare the industrial relevance of the technology to be utilized as a fabrication tool in the market. Meanwhile, all the researchers around the globe aim at a single goal, which is the development of “Proof of Concept” devices and applications. Thus, here in this dissertation the implementation of the inkjet printing technology as a digital fabrication tool is exploited to manufacture and up-scale the printed electronic products, which can show an industrial relevance to the commercial market. The main motivation why printed electronics is in great demand (scientific point of view) and has intensely emerged in the last decades, is because of the primary challenges faced in the fabrication process steps of the µ-electronics society. It is know that the classically fabricated µ-electronic products are in the market since long time due to their high reliability, consistent performance and defined applications in circuitry. But, what cannot be ignored is the involved fabrication steps promote several demerits such as the in-flexibility towards the fabrication process, material wastage, in-ability to up-scale into larger areas and huge quantities, and physical rigidity. Some of these mentioned problems are commonly seen e.g. spin coating, chemical vapor-phase deposition, physical vapor-phase deposition, atomic layer deposition and sputtering fabrication technologies. In this present dissertation, on the contrary, the challenges linked with the manufacturing process of the µ-electronic devices using the inkjet technology are focused and attempts are made to counteract them. Some of the foreseen challenges are: A. process workflow adaptation in device manufacturing; B. validation and evaluation of device performance; C. industrializing the inkjet technology (manufacturing µ-electronics in massive quantities); D. evaluating the fabrication yield of printed devices; D. Generating statistics regarding reliability and scalability; and E. demonstrating tolerances in electronic performances. These are definitely the challenges which must be overcome, and these key research points are addressed in the dissertation.