Orientador: Plamen Emilov Kochloukov / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Matemática, Estatística e Computação Científica / Made available in DSpace on 2018-08-20T11:39:36Z (GMT). No. of bitstreams: 1 Reis_JulioCesardos_D.pdf: 2452563 bytes, checksum: 63f8b1d463a36f74d57c1d71769dc9ae (MD5) Previous issue date: 2012 / Resumo: Na presente tese, fornecemos bases das identidades polinomiais graduadas de...Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digital / Abstract: In this PhD thesis we give bases of the graded polynomial identities of...Note: The complete abstract is available with the full electronic document / Doutorado / Matematica / Doutor em Matemática

The Division of Computer Engineering at Linköping's university is currently researching the possibility to create a highly parallel DSP platform, that can keep up with the computational needs of upcoming standards for various applications, at low cost and low power consumption. The architecture is called ePUMA and it combines a general RISC DSP master processor with eight SIMD co-processors on a single chip. The master processor will act as the main processor for general tasks and execution control, while the co-processors will accelerate computing intensive and parallel DSP kernels.This thesis investigates the performance potential of the co-processors by implementing matrix algebra kernels for QR decomposition, LU decomposition, matrix determinant and matrix inverse, that run on a single co-processor. The kernels will then be evaluated to find possible problems with the co-processors' microarchitecture and suggest solutions to the problems that might exist. The evaluation shows that the performance potential is very good, but a few problems have been identified, that causes significant overhead in the kernels. Pipeline mismatches, that occurs due to different pipeline lengths for different instructions, causes pipeline hazards and the current solution to this, doesn't allow effective use of the pipeline. In some cases, the single port memories will cause bottlenecks, but the thesis suggests that the situation could be greatly improved by using buffered memory write-back. Also, the lack of register forwarding makes kernels with many data dependencies run unnecessarily slow.