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Substrate coupling macromodel for lightly doped CMOS processesKoteeswaran, Mohanalakshmi 16 September 2002 (has links)
A scalable macromodel for substrate noise coupling in lightly doped substrates
with and without a buried layer has been developed. This model is based on
Z-parameters and is scalable with contact size and separation. This model requires
process dependent parameters that can be extracted easily from a small number of
device simulations or measurements. Once these parameters are known, the model
can be used for any spacing between the injecting and sensing contacts and for different
contact geometries. The model is validated with measurements for a lightly
doped substrate with a buried layer and predicts the substrate resistance values to
within 12%. The substrate resistances obtained using the model are also in close
agreement with the three-dimensional simulations for a lightly doped substrate. / Graduation date: 2003
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Design of current-mode track and hold circuitsChennam, Madhusudhan 07 June 2002 (has links)
A differential current-mode track-and-hold (T/H) amplifier is used to sample
an analog input signal. A new closed-loop current-mode architecture has been
developed that overcomes the stability problems associated with closed-loop architectures.
The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly
CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB
with an input signal frequency of 100KHz and 10MHz, respectively. This is the best
performance reported to date for a CMOS implementation. / Graduation date: 2003
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Analysis and design of CMOS RF LNAs with ESD protectionChandrasekhar, Vinay 01 April 2002 (has links)
An analysis that accounts for the effect of standard electrostatic discharge
(ESD) structures on critical LNA specifications of noise figure, input matching and
gain is presented. It is shown that the ESD structures degrade LNA performance
particularly for higher frequency applications. Two LNAs, one with ESD protection
and one without, which operate at 2.4 GHz have been fabricated in a 0.l5��m CMOS
process. The LNAs feature one of the best reported performances for CMOS LNAs
to date. The LNA with ESD protection achieves a gain of 12dB, a NF of 2.77dB
and an IIP3 of 2.4dBm with a power consumption of 4.65mW. The LNA without
ESD protection achieves a gain of 14dB, a NF of 2.36dB and an 11P3 of -2.2dBm
with a power consumption of 4.65mW. / Graduation date: 2002
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Operational amplifier bandwidth extension using negative capacitance generation /Genz, Adrian P., January 2006 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 53-54).
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A high-throughput divider based on output prediction logic /Guo, Xinyu, January 2006 (has links)
Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 98-102).
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Desensitized CMOS low noise amplifiers /Banerjee, Gaurab, January 2006 (has links)
Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 97-101).
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Multi-standard low-power base-band digital receiver, enhanced for HSDPA /Martelli, Chiara, January 2006 (has links)
Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16683. / Summary in Italian and English; text in English. Includes bibliographical references (p. 171-177).
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Quantum-mechanical modeling of transport parameters for MOS devices /Höhr, Timm, January 2006 (has links)
Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16228. / Summary in German and English, text in English. Includes bibliographical references (p. 123-132).
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Analysis of power requirements inside of NMOS integrated circuitsWilson, Jeffrey 03 1900 (has links) (PDF)
M.S. / Computer Science / Software has been developed to analyze the power requirements of NMOS integrated circuits. Power usage is calculated for the entire chip. Current flow through each metal segment of VDD and GND lines is also calculated. The program, Pwranal, takes CIF format files as input and analyzes DC power requirements in the IC. Power estimates are worst case numbers. Power requirements may be less than the estimate but will not be more. Heuristics based on circuit topology are used to generate a more refined estimate of power needs. Initial values of nodes can be specified to provide an even more refined worst case power estimate. Current density is calculated and warning messages are displayed when it exceeds safe values. Maximum voltage drop in the VDD and GND lines is also calculated. An output summary is sent to the terminal. An optional CIF format output file can also be generated that contains detailed information about power distribution within the circuit.
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High accuracy CMOS switched-current ladder filtersHoei, Jung-sheng 07 May 1991 (has links)
Clock-feedthrough effects, channel-length modulation and device mismatch are
the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these
non-ideal effects are analyzed. A high-performance current mirror, namely regulated
cascode current mirror, which eliminates drain voltage variation problem is introduced.
By using this current mirror as a basic memory cell, a clock-feedthrough cancellation
circuit is developed, which ideally solves the clock-feedthrough and drain voltage
variation problems. A fifth-order SI lowpass Chebyshev ladder filter is built using the
proposed cancellation circuit and implemented in a two-micron P-well standard digital
CMOS process by MOSIS. Another emerging technique, dynamic current mirrors or
current copiers, is introduced. Improved dynamic current mirror cell and dynamic
current mirror-based integrators have been developed. / Graduation date: 1992
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