Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Includes bibliographical references (leaves 91-93).

No description available.

• Abstract Integrated digital imaging systems are widely used in consumer electronics today. Current digital image sensors have a linear respeiiSt. The limited dynamic range of linear digital image sensors results in saturation when the input dynamic range of the scene is larger than that of the camera. This limitation could be overcome using pixels with an output that is proportional to the logarithm of the detected photocurrent. Conventional CMOS pixels with a logarithmic response, using a transistor operating in the sub-threshold region, are capable of capturing wide dynamic range scenes with more than six decades of illumination intensity. But these pixels suffer from fixed pattern noise, slow response and low sensitivity. A five transistor (5T) pixel circuit for a standard 0.35-fLm CMOS process which integrates the photocurrent linearly and capable of a logarithmic response is described in the thesis. A key component of the 5T pixel is a time-dependent reference voltage. This voltage is applied to the gate of one of the transistors inside each pixel in the array for the duration of the exposure to generate a logarithmic response. A model derived to generate the reference voltage is described. Improvements were made to the reference voltage model to take into consideration the non-ideal effects such as charge feedthrough and threshold voltage variations. A potential problem associated with successfully tonemapping low photo currents with the 5T pixel has been described and a method to calculate the optimal value of reference current Iret proposed. This was shown to lead to an optimum photoresponse. Measurement results from fabricated 1-D and 2-D arrays of 5T pixels are presented and analysed. An overall DR of 97-dB (almost 5 decades) has been achieved from 100 mlux to 6.7 Klux. The slope of the logarithmic photoresponse was shown to be adjustable and controlled by the slope parameter S in the reference voltage model. A large output swing of over 1 V due to the large photoresponse slope in the logarithmic region results in greater signal-to-noise ratio compared to the conventional logarithmic pixel based on the subthreshold transistor operation (60 m V/decade). Digital and analogue reference voltage generating techniques are described with circuits implemented in 0.35-fLm CM OS process. Finally, a 5T NMOS pixel that is capable of WDR imaging with superior low-light performance (23 mlux) and greater DR (1l0-dB) than the 5T PMOS pixel is described. [ a

University of Macau / Faculty of Science and Technology. / Department of Electrical and Computer Engineering

by Man-chung Suen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves [123]-[126]). / Acknowledgement --- p.ii / Abstract --- p.iii / List of Tables --- p.vii / List of Figures --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Approach to Find the Equivalent Models --- p.5 / Chapter 2.1 --- Scattering Parameters of the Microstrip Structure --- p.5 / Chapter 2.2 --- Optimization Process --- p.7 / Chapter 2.3 --- Summary --- p.8 / Chapter 3 --- Microstrip Discontinuities Being Modelled --- p.9 / Chapter 3.1 --- Right-Angled Bend --- p.9 / Chapter 3.2 --- T-Junction --- p.10 / Chapter 3.3 --- Tapered Line --- p.10 / Chapter 4 --- Deficiency of Lumped Equivalent Circuits --- p.13 / Chapter 4.1 --- Scattering Parameter of the T-Network --- p.13 / Chapter 4.2 --- Optimization Result for the T-Network --- p.14 / Chapter 4.3 --- Summary --- p.15 / Chapter 5 --- Proposed Wideband Equivalent Circuits --- p.17 / Chapter 5.1 --- Model of a Uniform Non-Homogeneous Microstrip Line --- p.17 / Chapter 5.2 --- Right-Angled Bend --- p.22 / Chapter 5.2.1 --- Circuit 1L --- p.24 / Chapter 5.2.2 --- Circuit 2L --- p.25 / Chapter 5.2.3 --- Circuit 3L --- p.26 / Chapter 5.2.4 --- Circuit 4L --- p.27 / Chapter 5.3 --- T-Junction --- p.28 / Chapter 5.3.1 --- Circuit IT --- p.28 / Chapter 5.3.2 --- Circuit 2T --- p.31 / Chapter 5.3.3 --- Circuit 3T --- p.31 / Chapter 5.3.4 --- Circuit 4T --- p.34 / Chapter 5.4 --- Tapered Line --- p.36 / Chapter 5.4.1 --- Circuit It -n =3 --- p.37 / Chapter 5.5 --- Summary --- p.38 / Chapter 6 --- Performance of the Equivalent Circuits --- p.39 / Chapter 6.1 --- Right-Angled Bend --- p.40 / Chapter 6.1.1 --- Without Conductor Loss --- p.40 / Chapter 6.1.2 --- With Conductor Loss --- p.48 / Chapter 6.2 --- T-Junction --- p.49 / Chapter 6.2.1 --- Without Conductor Loss --- p.53 / Chapter 6.2.2 --- With Conductor Loss --- p.63 / Chapter 6.3 --- Tapered Line --- p.69 / Chapter 6.3.1 --- Without Conductor Loss --- p.69 / Chapter 6.3.2 --- With Conductor Loss --- p.72 / Chapter 6.4 --- Summary --- p.73 / Chapter 7 --- Modelling Performance Using TEM Approximation --- p.77 / Chapter 7.1 --- Right-Angled Bend --- p.77 / Chapter 7.1.1 --- Without Conductor Loss --- p.78 / Chapter 7.1.2 --- With Conductor Loss --- p.87 / Chapter 7.2 --- T-Junction --- p.92 / Chapter 7.2.1 --- Without Conductor Loss --- p.92 / Chapter 7.2.2 --- With Conductor Loss --- p.104 / Chapter 7.3 --- Tapered Line --- p.115 / Chapter 7.3.1 --- Without Conductor Loss --- p.116 / Chapter 7.3.2 --- With Conductor Loss --- p.117 / Chapter 7.4 --- Summary --- p.117 / Chapter 8 --- Conclusion --- p.120 / Bibliography --- p.123

Mak Wing-sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaf [68]). / Abstracts in English and Chinese. / List of Figures --- p.I / List of Tables --- p.III / ACKNOWLEDGMENTS / ABSTRACT / Chapter Chapter I --- Introduction / Chapter 1.1 --- Introduction - Low Power --- p.I-1 / Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1 / Chapter 1.2.1 --- Static Power Dissipation --- p.I-2 / Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5 / Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8 / Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10 / Chapter 1.4 --- Objective of the Project --- p.I-10 / Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic / Chapter 2.1 --- Low Power Design --- p.II-12 / Chapter 2.2 --- Adiabatic Switching --- p.II-12 / Chapter 2.3 --- Adiabatic Logic --- p.II-14 / Chapter 2.4 --- History of Adiabatic Logic --- p.II-17 / Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter / Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18 / Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20 / Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22 / Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23 / Chapter Chapter IV --- Power Clock Generator / Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24 / Chapter 4.2 --- Power Clock Generator / Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV / Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27 / Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier / Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32 / Chapter 5.2 --- Structure of Multiplier --- p.V-34 / Chapter Chapter VI --- Simulations / Chapter 6.1 --- AqsCMOS Inverter / Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38 / Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39 / Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI / Chapter 6.2 --- Power Clock Generator --- p.VI -42 / Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45 / Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46 / Chapter ChapterVII --- evaluations / Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51 / Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus / Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54 / Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55 / Chapter 7.2.3 --- Input Current Measurement --- p.VII -58 / Chapter 7.3 --- Power Measurement --- p.VII -63 / Chapter Chapter VIII --- Conclusions and Fiirthfr Developments / Chapter 8.1 --- Conclusions --- p.VIII -65 / Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65 / Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65 / Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66 / Chapter 8.2 --- Further Development --- p.VIII -66 / Appendix I micro-photography of aqscmos multiplier / Appendix II micro-Photography of CMOS multiplier / Appendix III micro-photography of AqsCMOS inverter chain testing modules / Appendix IV power - meter simulation approach / Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers / Reference

Ku Man-Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 86-87). / Chapter 1. --- Introduction / Chapter 1.1. --- Introduction --- p.1 / Chapter 1.2. --- Power Noise --- p.2 / Chapter 1.3. --- High Speed Output Driver Design --- p.3 / Chapter 2. --- Power Bus Noise Analysis / Chapter 2.1. --- Introduction --- p.7 / Chapter 2.2. --- The Power bus model of a packed VLSI chip --- p.7 / Chapter 2.3. --- The effects of bonding wire on Power bus --- p.11 / Chapter 2.4. --- Noise analysis of multi-driver switching --- p.15 / Chapter 3. --- Effects of Power bus noise / Chapter 3.1. --- Introdcution --- p.22 / Chapter 3.2. --- Digital noise definition --- p.22 / Chapter 3.3. --- Static CMOS Inverter --- p.23 / Chapter 3.4. --- Dynamic gate --- p.32 / Chapter 4. --- Output Driver Design / Chapter 4.1. --- Introduction --- p.37 / Chapter 4.2. --- Optimum Discharge Current Waveform --- p.37 / Chapter 4.3. --- Simple Inverter Output driver --- p.40 / Chapter 4.4. --- Weighted and Distributed Driver --- p.42 / Chapter 4.5. --- Short circuit current prevention circuit --- p.50 / Chapter 5.6. --- Adaptive output driver --- p.52 / Chapter 5. --- Test chip Implementation / Chapter 5.1. --- Introduction --- p.57 / Chapter 5.2. --- Output Driver Circuit Design --- p.57 / Chapter 5.3. --- Simulation Results --- p.62 / Chapter 5.4. --- Test chip circuit --- p.65 / Chapter 5.5. --- Physical design --- p.67 / Chapter 6. --- Test Chip evaluation / Chapter 6.1. --- Introduction --- p.75 / Chapter 6.2. --- Rise time and overshoot Test --- p.76 / Chapter 6.3. --- Switching noise --- p.79 / Chapter 6.4. --- Driving Test --- p.82 / Chapter 7. --- Conslusions --- p.84 / Chapter 8. --- References --- p.86 / Chapter 9. --- Appendix A --- p.88 / Chapter 10. --- Appendix B --- p.91 / Chapter 11. --- Appendix C --- p.100 / Chapter 12. --- Appendix D --- p.101 / Chapter 13. --- Appendix E --- p.102

Ho Kin-Pui. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 92-95). / Abstracts in English and Chinese. / Abstract --- p.2 / 摘要 --- p.4 / Acknowledgements --- p.5 / Table of Contents --- p.6 / List of Figures --- p.10 / List of Tables --- p.14 / Chapter Chapter 1 --- Introduction --- p.15 / Overview --- p.15 / Objective --- p.17 / Thesis Organization --- p.17 / Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19 / Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19 / Chapter 2.1.1 --- Input Differential Voltage Range --- p.19 / Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20 / Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20 / Chapter 2.1.4 --- Input Offset Voltage --- p.20 / Chapter 2.1.5 --- Gain Bandwidth Product --- p.21 / Chapter 2.1.6 --- Phase Margin --- p.22 / Chapter 2.1.7 --- Slew Rate --- p.22 / Chapter 2.1.8 --- Settling Time --- p.23 / Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23 / Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24 / Chapter 2.2.1 --- Overview --- p.24 / Chapter 2.2.2 --- Miller Compensation --- p.25 / Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27 / Chapter 3.1 --- Introduction --- p.27 / Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28 / Chapter 3.2.1 --- Circuit Description --- p.29 / Chapter 3.2.2 --- Small Signal analysis --- p.32 / Chapter 3.2.3 --- Simulation Results --- p.34 / Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Frequency Response --- p.39 / Chapter 4.2.1 --- Gain-bandwidth product --- p.40 / Chapter 4.2.2 --- Right half complex plane zero --- p.40 / Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42 / Chapter 4.3 --- Components Sizing --- p.47 / Chapter 4.4 --- Circuit Simulation --- p.48 / Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Working principle of the proposed circuit --- p.54 / Chapter 5.2.1 --- The introduction of nulling resistor --- p.55 / Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55 / Chapter 5.2.3 --- Small Signal Analysis --- p.57 / Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59 / Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60 / Chapter 5.2.6 --- Stability Conditions --- p.63 / Chapter 5.3 --- Performance Comparison --- p.67 / Chapter 5.4 --- Conclusion: --- p.70 / Chapter 5.4.1 --- Circuit Modifications: --- p.70 / Chapter 5.4.2 --- Advantages: --- p.71 / Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72 / Chapter 6.1 --- Introduction --- p.72 / Chapter 6.2 --- Transistor Layout Techniques --- p.72 / Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72 / Chapter 6.2.2 --- Common-Centroid Structure --- p.73 / Chapter 6.3 --- Layout Techniques of Passive Components --- p.74 / Chapter 6.3.1 --- Capacitor Layout --- p.74 / Chapter 6.3.2 --- Resistor Layout --- p.75 / Chapter Chapter 7 --- Measurement Results --- p.77 / Chapter 7.1 --- Overview --- p.77 / Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77 / Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77 / Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80 / Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80 / Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80 / Chapter 7.3.3 --- Gain Band width Measurement --- p.81 / Chapter 7.3.4 --- DC Gain measurement --- p.85 / Chapter 7.3.5 --- Slew Rate Measurement --- p.87 / Chapter 7.3.6 --- Phase Margin --- p.88 / Chapter 7.3.7 --- Performance Summary --- p.89 / Chapter Chapter 8 --- Conclusions --- p.90 / Chapter Chapter 9 --- Appendix --- p.96

by Cheuk-Him, To. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / Abstract also in Chinese. / ACKNOWLEDGMENT --- p.I / ABSTRACT (ENGLISH) --- p.II / ABSTRACT (CHINESE) --- p.III / CONTENTS --- p.IV / TABLE OF FIGURES --- p.VI / Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Different types of DCO --- p.1-2 / Chapter 1.2.1 --- Divided by N counter --- p.1-2 / Chapter 1.2.2 --- Increment-decrement counter --- p.1-2 / Chapter 1.2.3 --- Controlled delay ring oscillator --- p.1-4 / Chapter 1.3 --- Problems suffered from these circuits --- p.1-4 / Chapter 1.4 --- Characteristics of the proposed circuit --- p.1-5 / Chapter CHAPTER 2 --- BACKGROUND THEORY --- p.2-1 / Chapter 2.1 --- Ring Oscillator --- p.2-1 / Chapter 2.2 --- Differential Pair --- p.2-1 / Chapter 2.3 --- Injection Locked Oscillator (ILO) --- p.2-2 / Chapter 2.4 --- Digital Controlled Oscillator --- p.2-3 / Chapter CHAPTER 3 --- DESIGN --- p.3-1 / Chapter 3.1 --- Circuit Description --- p.3-1 / Chapter 3.1.1 --- D/A converter --- p.3-2 / Chapter 3.1.2 --- Injection Locked Oscillator (ILO) --- p.3-3 / Chapter 3.2 --- Design Characteristics --- p.3-5 / Chapter 3.2.1 --- D/A converter --- p.3-5 / Chapter 3.2.2 --- ILO --- p.3-7 / Chapter 3.2.3 --- Physical Design (Layout Drawing) --- p.3-8 / Chapter CHAPTER 4 --- RESULTS --- p.4-1 / Chapter 4.1 --- Chip1 --- p.4-1 / Chapter 4.1.1 --- Simulation --- p.4-3 / Chapter 4.1.2 --- Measurement --- p.4-15 / Chapter 4.1.3 --- Evaluation --- p.4-23 / Chapter 4.2 --- Chip2 --- p.4-25 / Chapter 4.2.1 --- Simulation --- p.4-25 / Chapter 4.2.2 --- Measurement --- p.4-36 / Chapter 4.2.3 --- Evaluation --- p.4-47 / Chapter CHAPTER 5 --- CONCLUSION --- p.5-1 / REFERENCES: --- p.1 / APPENDIX: --- p.1

by Kelvin Cheung Ka Wai. / Thesis submitted in: June 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / ACKNOWLEDGEMENTS --- p.i / ABSTRACT --- p.ii / TABLE OF CONTENTS --- p.iii / LIST OF FIGURES --- p.vi / TIST OF TABLES --- p.viii / Chapter 1. --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Objective --- p.1-1 / Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1 / Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1 / Chapter 1.3.2 --- Dynamic logic --- p.1-2 / Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4 / Chapter 1.4.1 --- Static power dissipation --- p.1 -4 / Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6 / Chapter 1.4.2.1 --- Short circuit current --- p.1 -6 / Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6 / Chapter 1.4.2.3 --- Total power consumption --- p.1-8 / Chapter 1.5 --- Adiabatic Logic --- p.1-8 / Chapter 1.5.1 --- Low power electronics --- p.1-8 / Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9 / Chapter 1.6 --- Resources --- p.1-10 / Chapter 1.6.1 --- Computing instrument --- p.1-10 / Chapter 1.6.2 --- CAD tools --- p.1-10 / Chapter 1.6.3 --- Fabrication --- p.1-11 / Chapter 1.7 --- Organisation of the Thesis --- p.1-11 / Chapter 2. --- BACKGROUND THEORIES --- p.2-1 / Chapter 2.1 --- Limit of energy dissipation --- p.2-1 / Chapter 2.2 --- Reversible Electronics --- p.2-1 / Chapter 2.2.1 --- Reversibility --- p.2-1 / Chapter 2.2.2 --- Adiabatic Switching --- p.2-3 / Chapter 2.2.2.1 --- Conventional Charging --- p.2-3 / Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4 / Chapter 2.2.3 --- Reversible devices --- p.2-5 / Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6 / Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1 / Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1 / Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1 / Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2 / Chapter 3.2 --- Redistribution of Charge --- p.3-3 / Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4 / Chapter 3.3.1 --- False reversible inverter --- p.3-4 / Chapter 3.3.2 --- Adiabatic inverter --- p.3-5 / Chapter 3.3.3 --- Effective capacitance --- p.3-7 / Chapter 3.3.4 --- Logic alignment --- p.3-8 / Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10 / Chapter 3.3.5.1 --- Compensated cascading --- p.3-10 / Chapter 3.3.5.2 --- Balanced cascading --- p.3-11 / Chapter 3.4 --- Frequency Control --- p.3-12 / Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13 / Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1 / Chapter 4.1 --- Design --- p.4-1 / Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1 / Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2 / Chapter 4.1.3 --- Layout --- p.4-3 / Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3 / Chapter 4.1.3.2 --- Transistor pair --- p.4-9 / Chapter 4.2 --- Capacitance Calculation --- p.4-9 / Chapter 4.2.1 --- Non-switching device --- p.4-10 / Chapter 4.2.2 --- Switching device --- p.4-11 / Chapter 4.3 --- Clocking Scheme --- p.4-13 / Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14 / Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1 / Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2 / Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3 / Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4 / Chapter 5.3.1 --- Transistor sizing --- p.5-5 / Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5 / Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6 / Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6 / Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7 / Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9 / Chapter 6. --- EVALUATION --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Simulation Results --- p.6-1 / Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1 / Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4 / Chapter 6.2.2.1 --- Functional evaluation --- p.6-4 / Chapter 6.2.2.2 --- Performance evaluation --- p.6-6 / Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8 / Chapter 6.3.1 --- Layout --- p.6-8 / Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10 / Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11 / Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13 / Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14 / Chapter 6.3.5.1 --- DC characteristics --- p.6-14 / Chapter 6.3.5.2 --- AC characteristics --- p.6-14 / Chapter 6.3.6 --- Power dissipation --- p.6-17 / Chapter 7 --- CONCLUSIONS --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Design --- p.7-1 / Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1 / Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2 / Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2 / Chapter 7.3 --- Function --- p.7-3 / Chapter 7.4 --- Power Dissipation --- p.7-3 / Chapter 7.5 --- Discussion --- p.7-3 / Chapter 7.6 --- Further Development --- p.7-3 / Chapter 7.7 --- Conclusion --- p.7-4 / Chapter 8. --- REFERENCES --- p.8-1 / APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1 / APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1