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Design of CMOS switched-current filtersFiez, Theresa S. 14 June 1990 (has links)
The design and implementation of Switched-Current (SI) ladder filters is
described. SI filters require only a standard digital CMOS process and the power
supply voltage requirement is low. SI circuits also can be potentially operated at
higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance
wideband nodes of the current mirrors. A simple method has been developed to
design SI ladder and biquadratic fllters with maximum dynamic range that leverages
the well-established design methodologies of SC filters. A standard digital 2-micron
n-well CMOS process has been used to implement two high-order ladder filters and
two biquadratic filters. Simulations accurately predict the measured results of the
first integrated SI filters. The area and power dissipation are comparable to the
switched-capacitor technique.
Analysis of the factors that effect dynamic range in SI filters is presented.
The factors that contribute to harmonic distortion in the current-mode circuits are
characterized and the relationships to maximum signal size are established. Using
measurements of the input-referred noise from SI filters, the dynamic range is
obtained. / Graduation date: 1991
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A token caching waiting-matching unit for tagged-token dataflow computersTraylor, Roger L. 03 May 1991 (has links)
Computers using the tagged-token dataflow model are among the best candidates
for delivering extremely high levels of performance required in the future. Instruction
scheduling in these computers is determined by associatively matching data-bearing
tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens
with matching contexts are forwarded to an instruction while non-matching tokens are
stored to await their matching partner.
Requirements of the W-M unit are exacting. Necessary token storage capacity
at each processing element (PE) is presently estimated to be 100,000 tokens. Since the
most often executed arithmetic instructions require two operands, the bandwidth of the
W-M unit must be approximately twice that of the ALU. The contradictory
requirements of high storage capacity and high memory bandwidth have compromised
the M-W units of previous dataflow computers limiting their speed.
However, tokens arriving at a PE exhibit strong temporal locality. This
naturally suggests the use of some caching technique. Using a recently developed
CAM memory structure as a base, a token caching scheme is described which allows
rapid, fully associative token matching while allowing a large token storage capacity.
The key to the caching scheme is a fast and compact, articulated, first-in, first-out,
content addressable memory (AFCAM) which allows associative matching and
garbage collection while maintaining temporal ordering. A new memory cell is
developed as the basis for the AFCAM in an advanced CMOS (Complementary Metal
Oxide Semiconductor) technology. The design of the cell is discussed as well as
electrical simulation results, verifying its operation and performance.
Finally, estimated system performance of a dataflow computer using the
caching scheme is presented. / Graduation date: 1991
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CMOS differential logic techniques for mixed-mode applicationsChee, San-hwa 12 July 1990 (has links)
Graduation date: 1991
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Hierarchical power optimization for ultra low-power digital systemsChoi, Kyu-Won 01 December 2003 (has links)
No description available.
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On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image SensorRobucci, Ryan 11 January 2005 (has links)
CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard CMOS processes which allow for mixed signal processing on-chip. A system-on-a-chip approach offers the ability to perform complex algorithms faster, in less space, and with lower power and noise. Our transform imager is an implementation of a mixed focal plane and peripheral computation imager which allows high fill factor with high computational rates at low power. However, in order to use the technology effectively a need to verify and further understand the behavior and of the pixel elements in this transform imager was needed. This thesis presents a study of the pixel elements and mismatches and errors in the pixel array of this imager. From there, a discussion about removing offsets and an implementation of a circuit to remove the largest offsets is shown. To further enhance performance, initial work to develop light adaptive readout circuits is presented. Finally, an overview is given of a newly designed one-megapixel transform imager with many design improvements.
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CMOS fingerprint sensor electrostatic modelingSoora, Praveen K., January 2000 (has links)
Thesis (M.S.)--West Virginia University, 2000. / Title from document title page. Document formatted into pages; contains viii, 94 p. : ill. (some col.). Vita. Includes abstract. Includes bibliographical references (p. 88-89).
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Design and study of phase locked loop for space applications in sub-micron CMOS technologyGhosh, Partha Pratim. January 2009 (has links)
Thesis (Ph.D.)--University of Texas at Arlington, 2009.
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Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrationMule, Anthony Victor, January 2004 (has links) (PDF)
Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by James D. Miendl. / Vita. Includes bibliographical references.
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Low voltage CMOS digital imaging architecture with device scaling considerations /Xu, Chen. January 2004 (has links)
Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
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Hierarchical power optimization for ultra low-power digital systemsChoi, Kyu-Won, January 2003 (has links) (PDF)
Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Abhijit Chatterjee. / Vita. Includes bibliographical references (leaves 127-145).
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