Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references. Also available in electronic version.

Thesis (Ph. D.)--Ohio State University, 2007. / Title from first page of PDF file. Includes bibliographical references (p. 104-107).

Thesis (Ph. D.)--University of Washington, 2000. / Vita. Includes bibliographical references (leaves 120-131).

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 118-126). Available also in a digital version from Dissertation Abstracts.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2008. / Includes bibliographical references (p. 94-97).

Research in biology and medicine depends heavily on what we can measure. Photoacoustic imaging techniques allow for imaging both structural and functional information simultaneously. Current photoacoustic imaging technology is limited by either the speed at which the images are formed or resolution of the images. By increasing the resonant frequency at which the transducers receive photoacoustic signals, the resolution of a photoacoustic tomography setup can be improved without compromising on imaging speed. Due to their size, the resulting transducers must be placed directly onto a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC). This thesis describes a fabrication flow and electronics design that opens the door to high speed, high resolution photoacoustic imaging. A microfabrication flow is developed to place high frequency polyvinylidene fluoride transducers onto an integrated circuit. A 1-D array of transducers are fabricated and characterized on a CMOS IC. The custom IC (TSMC 90 nm) is designed to amplify the signals coming from the small transducers using a proposed two-stage LNA. The circuit is electrically characterized before and after transducer fabrication showcasing the CMOS-compatible nature of the fabrication flow. The transducers and integrated circuit are characterized in a photoacoustic setup using two phantoms to verify the functionality of the system. Compared to similar systems, this system displays monolthically integrated transducers that receive broadband responses centered at 35 MHz with 140 bandwidth.

In modern deep-scaled CMOS technologies, various silicon-related pitfalls present challenges to the long-term performance of microprocessors. Such challenges include (1) local hot spots, which breach the thermal limitations of a microprocessor, and (2) transistor aging, especially NBTI, which degrades transistor threshold voltage, ultimately threatening the reliability of the entire memory block. In previous systems, the dummy circuit was placed next to the subject, where the dummy was frequently analyzed, and the readout was used to infer the condition of the target. Due to rapidly changing ambient conditions (e.g., temperature and voltage) and the potential scale of the target dimensions, such metrics may not accurately represent the condition of the target. Moreover, such temperature sensors and canary circuits occupy a significant area. Therefore, it would be highly preferable to monitor the target circuit in-situ, i.e., to sense the precise transistor at operation. It is also important to achieve an accurate sensing metric. When the temperature is analyzed, the readout should account for voltage and process variations. While sensing the aging degradation, the readout should account for voltage and temperature fluctuations. This would allow testing during in-field operation, while the circuits achieve area-efficiency. This research had two stages. One result of the first stage was a silicon test chip that was a compact temperature sensor. It involved a family of PTAT+CTAT sensor front-ends that unitized only 6 to 8 conventional CMOS logic devices, yielding a smaller sized chip. The sensor demonstrates accuracy within the target and achieves a 14.3x smaller foot print than preceding published designs. The second product of the first stage was a PMOS aging sensor used in 6T SRAM circuits. The test chip has a real SRAM array, integrated with the proposed PMOS NBTI sensor. It can sense real PMOS NBTI effects in any bit cell (in-situ) and provide robust readings of temperature and voltage (in-field). Intensive aging tests validated the proposed sensing technique. The second stage was focused on implementing the in-situ and in-field sensing techniques in a real processor. The MIPS microprocessor had a modified instruction cache (I$) and instruction set architecture. With the addition of new instruction aging sensing and minor modification of the circuits, the processor can execute aging sensing opportunistically to evaluate the aging level of its instruction cache. A software framework was developed and verified to estimate the retention voltage of the instruction cache over the lifetime of the chip. An area-efficient SoC was developed that could transform the instruction cache into an ambient temperature sensor. It had a physically unclonable function (PUF), and it was built with an area-saving technique similar to the earlier work. This thesis has four chapters. They are presented in chronological and they are aligned with the research described above.

In the last two decades, there has been considerable development for biosensor devices as the need to more efficient sensing systems is increasing for monitoring the progress of medicine and help with the early diagnosis of the pathogens and treatment of diseases that would reduce the cost of patient care. DNA sensors, in particular, have attracted attention due to their abundance of practical applications in clinical diagnoses and genetic information which increase the demand for DNA probes. On the other hand, the development of the oxide semiconductors thin film transistors (TFT) devices have been greatly increased, owing to their superior electrical properties, lower cost and large coverage areas. Building a bridge across biological elements and electronic interface using advanced (TFT) platforms are based on materials design and device architecture. Here, a solution-processed multi-layer metal oxide (TFT) is explored as a novel DNA sensor. The device engineering combines the novel hetero-structure metal oxide channel that can sustain a 2-dimensional electron gas (2DEG) which leads to a higher mobility and surface functionalization capacity to create an ultrasensitive, highly stable, and versatile DNA sensor. The prototype solid-state TFT sensor features a sub-10 nm-thick metal oxide heterojunction channel of a In2O3 and a top ZnO layer. The devices developed here rely on a pyrene-based molecule as the receptor unit that is known to intercalate into double stranded DNA with a very high-affinity constant and at very low concentration.

This study uses differential pass transistor methodology for implementing and evaluating Boolean functions. The main goal is investigation of CMOS and nMOS approaches in pass transistor logic design. Pass-transistor logic is most effective in the implementation of Boolean functions when the vectors are in the same format. It has been demonstrated that nMOS pass transistor logic driven by a control signal voltage above the V dd level offers a significant improvement in speed. nMOS pass transistorsalso offer less area consumption in comparison to the CMOS approach. The philosophy developed here has been used in the design of a program for the layout generation of pass transistor networks. This program has been applied to the design of a 4-to-1 multiplexer and an adder (sum and carry). The layout of the circuit sub-cell have been done using the program Magic, based on 3μ CMOS p-well technology.

No description available.