No description available.

This thesis describes the development of a minimally invasive integrated platform for all-optical neural stimulation and measurement (OptoSAM). The OptoSAM platform is a single mixed-signal complementary metal-oxide semiconductor (CMOS) chip. After design, the chip is postprocessed to contain the necessary optical filters and emitters to enable both fluorescent detection and neural stimulation. Finally, the chip is packaged in a probe form factor for minimally-invasive implantation into neural tissue. The thesis describes how the OptoSAM is engineered for two applications: optical fluorescent imaging on one hand and optogenetic stimulation on the other. For either application, constraints and tradeoffs are described that guide design specifications. For fluorescent neural detection, this thesis focuses on improvements made in lens-less image reconstruction and optical filtering. It describes circuit design for the lens-less, filter-less fluorescent imaging subsystem and characterizes the resulting imaging performance. The lack of on-chip filters precludes reliable imaging of fluorescent targets both in-vivo and ex-vivo. To address these limitations, the metal-insulator-metal angle sensitive pixel (MIMASP) is introduced, a novel nanophotonic structure that integrates lens-less imaging and optical filtering in an ultrathin (<5μm) frontend. The MIMASP offers three advantages over previously published angle sensitive pixels. First, it orthogonally modulates the detection light field for two arbitrary wavelengths, enabling the separation and detection of colors in the image. Secondly, each layer is constructed from optical long-pass filters, rejecting the blue excitation light. Third, an analytical framework is created that allows to optimize the ensemble image reconstruction resolution as a function of the available per-pixel geometries. The angle sensitive pixels are a promising lens-less imaging method for situations where both the number of pixels and the permitted device dimensions are extremely constrained. Equipped with the MIMASP frontend, the imager is demonstrated in scattering media to successfully separate fluorescent targets based on color, fluorescent lifetime and even environmental pH. The experiments are extended to fluorescent detection in ex-vivo acute brain slices. For optogenetic stimulation, we equip the OptoSAM platform with organic light emitting diodes (OLEDs) as thin-film emitters. In-vivo results show how the OLED probe can evoke neural activity in a fully scalable fashion. Using synchronized groups of OLEDs, large neural populations can be synchronously activated. Simultaneously, single neurons can be manipulated by emission from single OLEDs at a 25μm pitch. We demonstrate single-unit manipulation and separation of both pyramidal and interneurons. A custom flexible, transparent multi-electrode array (MEA) provides the electrophysiological recording for cross-validation in the deep-brain. Measurements show how local field potentials (LFPs) are evoked at both 300μm and 1.2mm deep, and how the LFP magnitude roll-off proves locality of the induced activity. Compared to previously published stateof- the-art, the OLED-on-CMOS approach provides a two orders of magnitude larger field of view (FoV) while improving resolution by 3×. Pixel pitch and count can be fully scaled to provide arbitrary fields of view and resolution. The OptoSAM platform proves a pathway towards behavioral studies in awake mice. These studies could address multiple brain regions independently with a single device insertion. This provides neuroscientists with the tools to study relationship between distant regions with single-neuron resolution. While the detection and stimulation are separately optimized and validated, the chip is a promising platform for future integration of both modalities. To this end, it proposes three future chip designs, each with their respective strengths. The proposals also provide potential solutions to the challenges associated with the design and fabrication. The thesis concludes with recommendations for future experiments, both for the OptoSAM platform and for future designs.

Testing of digital circuits ensures functionality and reliability of the circuits. Previous research has addressed the inadequacies of conventional test methods based on line stuck-at faults in testing CMOS circuits and has proposed new test methods. In this research, the effectiveness of propagation delay testing for open and short faults and supply current monitoring for short faults is investigated. Representative circuits are modeled and simulated over a wide range of fault severities. Factors, such as circuit and fault features, that affect test effectiveness are evaluated and analyzed. From the results, general conclusions are drawn and future research is proposed. / Master of Science

The traditional line stuck-at fault model does not properly represent transistor stuck-open (SOP) faults in complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of faulty circuits. The majority of integrated circuit manufacturers still rely on stuck-at test sets to test CMOS combinational circuits at the risk of some SOP faults not being detected. In this thesis we investigate two aspects regarding the detection of SOP faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequences of stuck-at test sets. The performance of the proposed method is compared with those of competing methods. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage. / Master of Science

No description available.

Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used. Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products. Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error. The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 95-98). Also available in electronic format on the Internet.

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

No description available.

Orientador: Jose Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T10:56:11Z (GMT). No. of bitstreams: 1 Amaral_WellingtonAvelinodo.pdf: 14948298 bytes, checksum: 62522f5a0f70fd9563d5ac2c4c4652e2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho teve como finalidade o projeto e prototipagem de uma referência de tensão CMOS (Complementary Metal Oxide Semiconductor) baseada na tensão de limiar do transistor MOS (Metal Oxide Semiconductor). A inovação apresentada neste trabalho é a utilização de uma arquitetura original e com alto desempenho. Nas medidas realizadas em laboratório o circuito apresentou uma variação de 11ppm/0C. Desempenho este comparável às referências do tipo bandgap. Também foi projetado um sensor de temperatura com coeficiente térmico igual a 1mV/0C. Portanto, dois circuitos foram enviados para fabricação (o circuito ceinv35 e o circuito ceinv66). O circuito ceinv35, utilizando suas estruturas de trimmer, pode operar como referência de tensão ou como sensor de temperatura. O circuito ceinv66 foi a principal configuração estudada. Ele utiliza um circuito extrator de Vth, um circuito de start-up e um amplificador operacional. O circuito extrator de Vth utiliza uma topologia inovadora. Nos dois circuitos (ceinv35 e ceinv66) foram utilizadas estruturas de trimmer para possibilitar ajustes externos. No capítulo de introdução é apresentado um "overview" dos circuitos utilizados como referência de tensão. São analisadas algumas referências do tipo bandgap e algumas técnicas usualmente utilizada para o projeto de referências de tensão CMOS. No capítulo 2 são analisados o princípio de funcionamento e todo o equacionamento do circuito proposto. No capítulo 3 são apresentados os resultados de simulação. O circuito ceinv35 apresentou um coeficiente térmico igual a 1mV/0C, funcionando ele como sensor de temperatura. Já operando como referência de tensão, a variação apresentada foi de 4:06ppm/0C. O circuito ceinv66 apresentou uma variação de apenas 3:14ppm/0C. O capítulo 4 cobre o projeto dos layouts dos circuitos. Eles foram projetados utilizando a tecnologia da AMS (Austria Microsystems) de comprimento mínimo de canal igual a 0:35_m. No capítulo 5 são apresentados os resultados da extração de parasitas dos circuitos. Após esta análise foi verificada a necessidade de reajuste dos circuitos, utilizando as estruturas de trimmer. No capítulo 6 são fornecidos os resultados experimentais dos dois circuitos. No capítulo 7 é apresentada uma alternativa para o projeto da referência de tensão sem a necessidade da utilização do circuito de start-up. Neste mesmo capítulo também é apresentada uma proposta de metodologia para projeto dos trimmers do circuito. No capítulo 8 são discutidas as inovações propostas neste trabalho e algumas conclusões sobre o projeto apresentado. / Abstract: The objective of this work is to design and prototype a CMOS voltage reference based on the threshold voltage of the MOS transistor. The innovation presented in this work is the use of an original architecture with high performance. In the laboratory measurements the circuit presented 11ppm/0C of variation. This performance is comparable to the bandgap references. A temperature sensor was also designed and presented a temperature coefficient of 1mV/0C. Therefore, two circuits were prototyped (the ceinv35 circuit and the ceinv66 circuit). The circuit ceinv35, using the trimmer structures, can operate as a voltage reference or a temperature sensor. The circuit ceinv66 was the main topology studied. It uses a Vth extractor circuit, a start-up circuit and an operational amplifier. The Vth extractor circuit uses an original topology. In both circuits (ceinv35 and ceinv66) were used trimmer structures to make possible off-chip adjusts. In the introduction chapter is presented an overview of the circuits used as voltage references. Some bandgap references and some techniques used to design CMOS voltage references are analyzed. In chapter 2 are shown the operation principles and the equations extracted of the proposed circuit. In chapter 3 are shown the simulation results. The circuit ceinv35 presented a temperature coefficient of 1mV/0C, working as a temperature sensor. On the other side, working as a voltage reference, the variation presented was 4:06ppm/0C. The circuit ceinv66 presented a variation of just 3:14ppm/0C. The chapter 4 covers the layout design of the circuits. The AMS (Austria Microsystems) technology with a minimum channel length of 0:35_m was used. In chapter 5 are presented the parasitic extraction simulations. After this analyses new adjusts were made in the circuits. The trimmers structures were used for this adjusts. In chapter 6 are provided the experimental results of both circuits. In chapter 7 is presented an alternative for the voltage reference design without using a start-up circuit. In this chapter is also presented a methodology for the trimmers design. In chapter 8 are discussed the proposed innovations and some conclusions about the design presented. / Universidade Estadual de Campi / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica