Developing high efficiency solar cells for lower manufacturing costs has been a key objective for photovoltaic researchers to drive down the levelized cost of energy for solar power. In this pursuit, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46% under concentrator and 32% under AM0. However, the expensive cost has made it challenging for III-V solar cells to compete with the mainstream Silicon (Si) technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch, polar on non-polar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to investigate heterogeneously integrated 1J GaAs solar cells on Si substrate using germanium (Ge) as an intermediate buffer layer that will address mitigation of defects and dislocations between GaAs active cell structure and Ge “virtual” substrate on Si. The all-epitaxial molecular beam epitaxy (MBE)-grown thin (<1 μm) hybrid GaAs/Ge “virtual” buffer approach provided 1J GaAs cell efficiency of ~10% on Si, as compared with cell structures with thick 3 μm GaAs buffers. Solar cell results were further corroborated with material analysis to provide a clear path for the reduction of performance limiting dislocations. The thin “Ge-on-Si” virtual buffer was then investigated comprehensively to understand the impact of the heterostructure on device performance. The growth, structural, morphological, and electrical transport properties of epitaxial thin-film Ge, grown by solid source MBE on Si using a two-step growth process, were investigated. High-resolution x-ray diffraction analysis demonstrated ~0.10% tensile strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt due to misfit dislocations at the Ge/Si heterointerface. Micro-Raman spectroscopic analysis further corroborated the strain-state of the Ge thin-film on Si. Cross-sectional transmission electron microscopy revealed the formation of a 90° Lomer dislocation network at the Ge/Si heterointerface, suggesting the rapid and complete relaxation of the Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphologies with surface roughness < 2 nm. Hall mobility measurements, performed within a temperature range of 77 K to 315 K, and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in the thin Ge epilayer. Additionally, capacitance- and conductance-voltage measurements were performed after fabricating the metal-oxide-semiconductor capacitors (MOS-Cs) in order to determine the effect of epilayer dislocation density on interfacial defect states (Dit), bulk trap density, and the energy distribution of Dit as a function of temperature for electronic device applications. Deep level transient spectroscopy was used to identify the location (within the Ge bandgap) of electrically active trap levels; however, no significant trap levels were detected. Finally, the extracted Dit values were benchmarked against previously reported Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained in this work were found to be comparable with other Ge MOS devices integrated on Si via alternative buffer schemes. The understanding gained from this comprehensive study of Ge-on-Si will help optimize the 1J GaAs on Si via thin Ge buffer approach, to enable a future of high efficiency low cost solar cells for terrestrial applications. / Master of Science / The global energy landscape is projected to change remarkably in the coming decades with dwindling carbon based resource reserves and escalating energy demands, necessitating large-scale adoption of cleaner alternatives, such as solar energy. However, for widespread commercial and domestic adoption of photovoltaics, the cost of solar generated electricity must become competitive with non-renewable resources such as oil or coal. Thus, achieving high efficiency solar cells and driving down cell costs are key research objectives of the photovoltaic (PV) community in order to become more self-sufficient in the energy sector. In this pursuit, III-V compound semiconductor-based solar cells have steadily outperformed all other PV technologies, but cost-prohibitive for terrestrial deployment. Si is the undisputed standard in the PV industry; thus, to make a significant step forward in the pursuit of high efficiency solar cells, a promising approach will be to integrate the superior properties of compound semiconductors with the mature technology of Si. This research systematically investigates the integration of high efficiency III-V cells with low cost, abundant Si substrates via a germanium (Ge) layer to unify the performance merits of III-V cells with the cost benefits and superior mechanical and thermal properties of Si. Concurrently, Ge has also emerged as a strong candidate to boost transistor performance at low operating voltages, primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. This research further delves into the structural and electrical properties of the Ge on Si structure. Overall, this research demonstrates the feasibility of the use of Ge directly integrated on Si for high efficiency solar cells and low-power electronic devices.

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science

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Thesis (PhD (Electric and Electronic Engineering))--University of Stellenbosch, 2007. / There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation. Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation. The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide. The trapped charges in the gate-oxide generate additional space charge fields at the oxide-substrate interface. After a sufficient dose, a large positive charge builds up, having the same effect as if a positive voltage was applied to the gate terminal. Therefore, the transistor source to drain current can no longer be controlled by the gate terminal and the device remains on permanently resulting in device failure. There are four processes involved in the radiation response of MOS devices. First, the ionizing radiation acts with the gate oxide layer to produce electron-hole pairs. Some fraction of the electron-hole pairs recombine depending on the type of incident particle and the applied gate to substrate voltage, i.e. the electric field. The mobility of the electron is orders of magnitude larger than that of the holes in the gate oxide, and is swept away very quickly in the direction of the gate terminal. The time for the electrons to be swept away is on the order of 1ps. The holes that escape recombination remain near their point of origin. The number of these surviving holes determines the initial response of the device after a short pulse of radiation. The cause of the first process, i.e. the presence of the electric field, is the main motivation for design method described in this dissertation. The second process is the slow transport of holes toward the oxide-silicon interface due to the presence of the electric field. When the holes reach the interface, process 3, they become captured in long term trapping sites and this is the main cause of the permanent threshold voltage shift in MOS devices. The fourth process is the buildup of interface states in the substrate near the interface The main contribution of this dissertation is the development of the novel Switched Modular Redundancy (SMR) method for mitigating the effects of space radiation on satellite electronics. The overall idea of the SMR method is as follows: A charged particle is accelerated in the presence of an electric field. However, in a solid, electrons will move around randomly in the absence of an applied electric field. Therefore if one averages the movement over time there will be no overall motion of charge carriers in any particular direction. On applying an electric field charge carriers will on average move in a direction aligned with the electric field, with positive charge carriers such as holes moving in the direction of field, and negative charge carriers moving in the opposite direction. As is the case with process one and two above. It is proposed in this dissertation that if we apply the flatband voltage (normaly a zero bias for the ideal NMOS transistor) to the gate terminal of a MOS transistor in the presence of ionizing radiation, i.e. no electric field across the gate oxide, both the free electrons and holes will on average remain near their point of origin, and therefore have a greater probability of recombination. Thus, the threshold voltage shift in MOS devices will be less severe for the gate terminal in an unbiased condition. The flatband conditions for the real MOS transistor is discussed in appendix E. It was further proposed that by adding redundancy and applying a resting policy, one can significantly prolong the useful life of MOS components in space. The fact that the rate of the threshold voltage shift in MOS devices is dependant on the bias voltage applied to the gate terminal is a very important phenomenon that can be exploited, since we have direct control and access to the voltage applied to the gate terminal. If for example, two identical gates were under the influence of radiation and the gate voltage is alternated between the two, then the two gates should be able to withstand more total dose radiation than using only one gate. This redundancy could be used in a circuit to mitigate for total ionizing dose. The SMR methodology would be to duplicate each gate in a circuit, then selectively only activating one gate at a time allowing the other to anneal during its off cycle. The SMR algorithm was code in the “C” language. In the proposed design methodology, the design engineer need not be concerned about radiation effects when describing the hardware implementation in a hardware description language. Instead, the design engineer makes use of conventional design techniques. When the design is complete, it is synthesized to obtain the gate level netlist in edif format. The edif netlist is converted to structural VHDL code during synthesis. The structural VHDL netlist is fed into the SMR “C” algorithm to obtain the identical redundant circuit components. The resultant file is also a structural VHDL netlist. The generated VHDL netlist or SMR circuit can then be mapped to a Field Programmable Gate Array (FPGA). Spacecraft electronic designers increasingly demand high performance microprocessors and FPGAs, because of their high performance and flexibility. Because FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including FPGAs covers a wide range of space applications, and consequently, they are the object of this study in order to implement and test the SMR algorithm. We apply the principles of reconfigurable computing to implement the Switched Modular Redundancy Algorithm in order to mitigate for Total Ionizing Dose (TID) effects in FPGA’s. It is shown by means of experimentation that this new design technique provides greatly improved TID tolerance for FPGAs. This study was necessary in order to make the cost of satellite manufacturing as low as possible by making use of Commercial off-the-shelf (COTS) components. However, these COTS components are very susceptible to the hazards of the space environment. One could also make use of Radiation Hard components for the purpose of satellite manufacturing, however, this will defeat the purpose of making the satellite manufacturing cost as low as possible as the cost of the radiation hard electronic components are significantly higher than their commercial counterparts. Added to this is the undesirable fact that the radiation hard components are a few generations behind as far as speed and performance is concerned, thus providing even greater motivation for making use of Commercial components. Radiation hardened components are obtained by making use of special processing methods in order to improve the components radiation tolerance. Modifying the process steps is one of the three ways to improve the radiation tolerance of an integrated circuit. The two other possibilities are to use special layout techniques or special circuit and system architectures. Another method, in which to make Complementary Metal Oxide Silicon (CMOS) circuits tolerant to ionizing radiation is to distribute the workload among redundant modules (called Switched Modular Redundancy above) in the circuit. This new method will be described in detail in this thesis.

Fluorescence based analysis is a fundamental research technique used in the life sciences. However, conventional fluorescence intensity measurements are prone to misinterpretation due to illumination and fluorophore concentration non-uniformities. Thus, there is a growing interest in time-resolved fluorescence detection, whereby the characteristic fluorescence decay time-constant (or lifetime) in response to an impulse excitation source is measured. The sensitivity of a sample’s lifetime properties to the micro-environment provides an extremely powerful analysis tool. However, current fluorescence lifetime analysis equipment tends to be bulky, delicate and expensive, thereby restricting its use to research laboratories. Progress in miniaturisation of biological and chemical analysis instrumentation is creating low-cost, robust and portable diagnostic tools capable of high-throughput, with reduced reagent quantities and analysis times. Such devices will enable point-of-care or in-the-field diagnostics. It was the ultimate aim of this project to produce an integrated fluorescence lifetime analysis system capable of sub-nano second precision with an instrument measuring less than 1cm3, something hitherto impossible with existing approaches. To accomplish this, advances in the development of AlInGaN micro-LEDs and high sensitivity CMOS detectors have been exploited. CMOS allows electronic circuitry to be integrated alongside the photodetectors and LED drivers to produce a highly integrated system capable of processing detector data directly without the need for additional external hardware. In this work, a 16x4 array of single-photon avalanche diodes (SPADs) integrated in a 0.35μm high-voltage CMOS technology has been implemented which incorporates two 9-bit, in-pixel time-gated counter circuits, with a resolution of 400ps and on-chip timing generation, in order to directly process fluorescence decay data. The SPAD detector can accurately capture fluorescence lifetime data for samples with concentrations down to 10nM, demonstrated using colloidal quantum dot and conventional fluorophores. The lifetimes captured using the on-chip time gated counters are shown to be equivalent to those processed using commercially available external time-correlated single-photon counting (TCSPC) hardware. A compact excitation source, capable of producing sub-nano second optical pulses, was designed using AlInGaN micro-LEDs bump-bonded to a CMOS driver backplane. A series of driver array designs are presented which are electrically contacted to an equivalent array of micro-LEDs emitting at a wavelength of 370nm. The final micro-LED driver design is capable of producing optical pulses of 300ps in width (full width half maximum, FWHM) and a maximum DC optical output power of 550μW, this is, to the best of our knowledge, the shortest reported optical pulse from a CMOS driven micro-LED device. By integrating an array of CMOS SPAD detectors and an array of CMOS driven AlInGaN micro-LEDs, a complete micro-system for time-resolved fluorescence analysis has been realised. Two different system configurations are evaluated and the ability of both topologies to accurately capture lifetime data is demonstrated. By making use of standard CMOS foundry technologies, this work opens up the possibility of a low-cost, portable chemical/bio-diagnostic device. These first-generation prototypes described herein demonstrate the first time-resolved fluorescence lifetime analysis using an integrated micro-system approach. A number of possible design improvements have been identified which could significantly enhance future device performance resulting in increased detector and micro-LED array density, improved time-gate resolution, shorter excitation pulse widths with increased optical output power and improved excitation light filtering. The integration of sample handling elements has also been proposed, allowing the sample of interest to be accurately manipulated within the micro-environment during investigation.

This thesis focuses on the development of a low power energy harvesting system specifically targeted for wireless sensor nodes (WSN) and wireless body area network (WBAN) applications. The idea for the system is derived from the operation of a micro-grid and therefore is termed as a pico-grid and it is capable of simultaneously delivering power from multiple and multitype energy harvesters to the load at the same time, through the proposed parallel load sharing mechanism achieved by a voltage droop control method. Solar panels and thermoelectric generator (TEG) are demonstrated as the main energy harvesters for the system. Since the magnitude of the output power of the harvesters is time-varying, the droop gain in the droop feedback circuitry should be designed to be dynamic and self-adjusted according to this variation. This ensures that the maximum power is capable to be delivered to the load at all times. To achieve this, the droop gain is integrated with a light dependent resistor (LDR) and thermistor whose resistance varies with the magnitude of the source of energy for the solar panel and TEG, respectively. The experimental results demonstrate a successful variation droop mechanism and all connected sources are able to share equal load demands between them, with a maximum load sharing error of 5 %. The same mechanism is also demonstrated to work for maximum power point tracking (MPPT) functionality. This concept can potentially be extended to any other types of energy harvester. The integration of energy storage elements becomes a necessity in the pico-grid, in order to support the intermittent and sporadic nature of the output power for the harvesters. A rechargeable battery and supercapacitor are integrated in the system, and each is accurately designed to be charged when the loading in the system is low and discharged when the loading in the system is high. The dc bus voltage which indicates the magnitude of the loading in the system is utilised as the signal for the desired mode of operation. The constructed system demonstrates a successful operation of charging and discharging at specific levels of loading in the system. The system is then integrated and the first wearable prototype of the pico-grid is built and tested. A successful operation of the prototype is demonstrated and the load demand is shared equally between the source converters and energy storage. Furthermore, the pico-grid is shown to possess an inherent plug-and-play capability for the source and load converters. Few recommendations are presented in order to further improve the feasibility and reliability of the prototype for real world applications. Next, due to the opportunity of working with a new semiconductor compound and accessibility to the fabrication facilities, a ZnON thin film diode is fabricated and intended to be implemented as a flexible rectifier circuit. The fabrication process can be done at low temperature, hence opening up the possibility of depositing the device on a flexible substrate. From the temperature dependent I-V measurements, a novel method of extracting important parameters such as ideality factor, barrier height, and series resistance of the diode based on a curve fitting method is proposed. It is determined that the ideality factor of the fabricated diode is high (> 2 at RT), due to the existence of other transport mechanism apart from thermionic emission that dominates the conduction process at lower temperature. It is concluded that the high series resistance of the fabricated diode (3.8 kΩ at RT) would mainly hinder the performance of the diode in a rectifier circuit.

Point functionalized carbon nanotubes have recently demonstrated the ability to serve as single-molecule biosensors. Operating as single-molecule Field-Effect Transistors (smFET), the sensors have been used to explore activity ranging in scope from DNA hybridization kinetics to DNA polymerase functionality. High signal levels and an all-electronic label-free transduction mechanism make the smFET an attractive candidate for next-generation medical diagnostics platforms and high-bandwidth basic science research studies. In this work, carbon nanotubes are integrated onto a custom designed CMOS chip. Integration enables arraying many devices for measurement, providing the requisite scale-up for any commercial application of smFETs. Integration also provides substantial benefits towards achieving high bandwidths through the reduction of electrical parasitics. In a first exploitation of these high-bandwidth measurement capabilities, integrated devices are electrically characterized over a 1-MHz bandwidth. Functionalization through electrochemical oxidation of the devices is observed with microsecond temporal resolution, revealing complex reaction pathways with resolvable scattering signatures. High rate random telegraph noise (RTN) is observed in certain oxidized devices, further illustrating the temporal resolution of the integrated sensing platform.

This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.