Thesis (M.S.E.C.E. )--University of Massachusetts Amherst, 2008. / Includes bibliographical references (p. 84-88).

Thesis (M.S.)--Rochester Institute of Technology, 1992. / Typescript. Includes bibliographical references (leaves 65-68).

abstract: Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology. / Front-end power converters for nanosatellite applications demand better performance in accurate reference tracking because of the wide-range input voltage of the solar panels. The very tight output voltage requirements demand a robust, reliable, and high-efficiency converter. The control of such a converter is very complex and time consuming to design. Two commonly used control modes are current and voltage control. The design and implementation of a voltage controller for DC–DC power converter is simpler but compared to current mode controller, does not do provide for overcurrent protection. A single-ended primary inductance converter (SEPIC) was selected for this research work because of its ability to buck or boost the input voltage coupled with the ability to provide noninverting polarity with respect to the input voltage. Parameter values for the converter studied are used to analyse and design both the voltage and the current mode controllers for the nanosatellite front-end power converter. Output voltage reference tracking with step and ramp changes in the input voltage is evaluated in terms of the time taken to reach steady-state after the induced disturbances and either the overshoot or undershoot of the output voltage reference. The design of analogue pulse width modulation (PWM) study was carried out in order to drive the metal-oxide-semiconductor field-effect transistor (MOSFET) switch. For the two controllers, changes in the reference output voltage in response to load changes are also studied. An examination of the effects of solar radiation on the MOSFET switch was conducted; this switch is the main component of the front-end DC–DC power converter for a nanosatellite. At the more general level the examination also provided information on the response of the semiconductor technology in space application. The overall purpose of studying the MOSFET switch was to investigate the mechanisms that will facilitate its ability of switching ‘on’ and ‘off’ without failure as a result of solar radiation. The effects of solar radiation on MOSFET device in space, has resulted in more malfunctions of these devices in the past five years than over the preceding 40 years.

No description available.

abstract: Global industrialization and urbanization have led to increased levels of air pollution. The costs to society have come in the form of environmental damage, healthcare expenses, lost productivity, and premature mortality. Measuring pollutants is an important task for identifying its sources, warning individuals about dangerous exposure levels, and providing epidemiologists with data to link pollutants with diseases. Current methods for monitoring air pollution are inadequate though. They rely on expensive, complex instrumentation at limited fixed monitoring sites that do not capture the true spatial and temporal variation. Furthermore, the fixed outdoor monitoring sites cannot warn individuals about indoor air quality or exposure to chemicals at worksites. Recent advances in manufacturing and computing technology have allowed new classes of low-cost miniature gas sensor to emerge as possible alternatives. For these to be successful however, there must be innovations in the sensors themselves that improve reliability, operation, and their stability and selectivity in real environments. Three novel gas sensor solutions are presented. The first is the development of a wearable personal exposure monitor using all commercially available components, including two metal oxide semiconductor gas sensors. The device monitors known asthma triggers: ozone, total volatile organic compounds, temperature, humidity, and activity level. Primary focus is placed on the ozone sensor, which requires special circuits, heating algorithm, and calibration to remove temperature and humidity interferences. Eight devices are tested in multiple field tests. The second is the creation of a new compact optoelectronic gas sensing platform using colorimetric microdroplets printed on the surface of a complementary-metal-oxide-semiconductor (CMOS) imager. The nonvolatile liquid microdroplets provide a homogeneous, uniform environment that is ideal for colorimetric reactions and lensless optical measurements. To demonstrate one type of possible indicating system gaseous ammonia is detected by complexation with Cu(II). The third project continues work on the CMOS imager optoelectronic platform and develops a more robust sensing system utilizing hydrophobic aerogel particles. Ammonia is detected colorimetrically by its reaction with a molecular dye, with additives and surface treatments enhancing uniformity of the printed films. Future work presented at the end describes a new biological particle sensing system using the CMOS imager. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2020

Emerging transparent semiconducting oxide (TSO) materials have achieved their initial commercial success in the display industry. Due to the advanced electrical performance, TSOs have been adopted either to improve the performance of traditional displays or to demonstrate the novel transparent and flexible displays. However, due to the lack of feasible p-type TSOs, the applications of TSOs is limited to unipolar (n-type TSOs) based devices. Compared with the prosperous n-type TSOs, the performance of p-type counterparts is lag behind. However, after years of discovery, several p-type TSOs are confirmed with promising performance, for example, tin monoxide (SnO). By using p-type SnO, excellent transistor field-effect mobility of 6.7 cm2 V-1 s-1 has been achieved. Motivated by this encouraging performance, this dissertation is devoted to further evaluate the feasibility of integrating p-type SnO in p-n junctions and complementary metal oxide semiconductor (CMOS) devices. CMOS inverters are fabricated using p-type SnO and in-situ formed n-type tin dioxide (SnO2). The semiconductors are simultaneously sputtered, which simplifies the process of CMOS inverters. The in-situ formation of SnO2 phase is achieved by selectively sputtering additional capping layer, which serves as oxygen source and helps to balance the process temperature for both types of semiconductors. Oxides based p-n junctions are demonstrated between p-type SnO and n-type SnO2 by magnetron sputtering method. Diode operating ideality factor of 3.4 and rectification ratio of 103 are achieved. A large temperature induced knee voltage shift of 20 mV oC-1 is observed, and explained by the large band gap and shallow states in SnO, which allows minor adjustment of band structure in response to the temperature change. Finally, p-type SnO is used to demonstrating the hybrid van der Waals heterojunctions (vdWHs) with two-dimensional molybdenum disulfide (2D MoS2) by mechanical exfoliation. The hybrid vdWHs show excellent rectifying performance. Due to the ultra-thin nature of MoS2, the operation of hybrid vdWHs is gate-tunable, and we further discover such gate-tunability depends on the layer number of MoS2, i.e., the screening effect. The detailed study in such hybrid vdWHs provides valuable information for understanding the switching performance of junctions contain 2D materials.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21110号 / 工博第4474号 / 新制||工||1695(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 教授 白石 誠司 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24623号 / 工博第5129号 / 新制||工||1980(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 川上 養一, 准教授 浅野 卓 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM