Orientador: José Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-26T13:53:46Z (GMT). No. of bitstreams: 1 Tercariol_WalterLuis_D.pdf: 1322557 bytes, checksum: 4f45518a1a62907cd9a61afa627408c3 (MD5) Previous issue date: 2014 / Resumo: Este trabalho visa compilar três contribuições na melhoria dos projetos de reguladores de tensão com unidades de bombeamento de carga embutidos (células elevadoras de tensão Dickson - BC). A primeira aborda uma técnica inovadora de arranque na partida deste módulo elevador quando habilitado. Este projeto se refere à aceleração da inicialização do modulo BC, tendo como objetivo a diminuição do intervalo de tempo da rampa ascendente da tensão de saída Vo até atingir o nível alvo de regulação. A técnica consiste em gerenciar o aumento da freqüência do relógio de bombeamento entregue as unidades de bombeamento durante a fase de subida, quando a regulação estiver estabelecida o sistema se regenera voltando ao estado original de freqüência de bombeamento natural. Uma segunda proposta inovadora de projeto é referente à homogeneização e redução da aleatoriedade da ondulação da tensão de saída Vo, referente ao regulador com o modulo BC embutido, baseado em comparadores com trava, com proposta de redução do erro de comparação devido ao efeito aleatório durante o estagio de comparação comumente encontrado neste tipo de abordagem, a técnica consiste em suprimir o acoplamento capacitivo nocivo durante a fase de isolamento elétrico no processo de comparação mantendo o espelho de corrente do comparador na região de saturação. Esta técnica visa proporcionar uma redução significativa da capacitância de desacoplamento utilizada para filtragem da tensão Vo. Uma terceira e última contribuição é referente a uma inovadora técnica de medição indireta da tensão de saída Vo do regulador com módulo BC baseada em uma medida simples e precisa dos pares tensão da porta e fonte (VPS) e corrente elétrica do dreno (Idreno) de um dispositivo NMOS de alta tensão adicionado de modo que duas tensões conhecidas (preestabelecidas) são aplicadas na porta do dispositivo e as respectivas correntes de dreno são mensuradas e uma terceira desconhecida (oriunda do regulador elevador BC) desconhecida pode ser extrapolada de forma simples. Esta técnica visa ser útil para medição de reguladores de baixa potencia pois o carregamento do regulador (Vo) é quase nulo.Todas as inovações e melhorias propostas foram analisadas em veículos de teste (silício) e com as provas de conceito, feitas em simulações elétricas / Abstract: This work aims to compile contributions in improving designs based on voltage regulators with voltage elevator with built-in charge pump CP. The first deals with an innovative technique rump-up this module when enabled. This project refers to the acceleration of startup the CP module, aiming at the reduction of the period of stabilization of the ramp output voltage Vo to the level of regulation target. The technique is to manage increasing the frequency of pumping clock during the phase of rump up and when the setting established the system regenerates back to the original state pumping frequency. A second innovative project proposal was made on the homogenization and reduction of the ripple of the output voltage Vo, referring to the regulator with the |CP module, based on latch comparators , alignment error reduction proposal because of the random effect during the stage comparison commonly found in this type of approach, the technique is to remove the harmful capacitive coupling during electrical isolation phase on the comparison keeping the comparator current mirror in saturation region. This technique aims to provide a significant reduction in the decoupling capacitance used for filtering the voltage Vo. A third and final contribution is related to an innovative technique of indirect measurement of the output voltage Vo of the regulator module CP, based on a simple and accurate measure of the gate voltage and couples the drain electric current of a high voltage NMOS device / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

The development of new materials and processes for electronic devices has been driven by the integrated circuit (IC) industry since the dawn of the computer era. After several decades of '"Moore's Law"-type innovation, future miniaturization may be slowed down by materials and processing limitations. By way of comparison, the nascent field of flexible electronics is not driven by the smallest possible circuit dimension, but instead by cost and form-factor where features typical of 1970s CMOS (i.e., channel length - IO μm) will enable flexible electronic technologies such as RFID, e-paper, photovoltaics and health monitoring devices. In this thesis. cyclohexasilane is proposed and used as a key reagent in solution processing of poly-Si and Co-Si thin films with the former used as the active layer in thin film transistors (TFTs) and the latter as the gate metal in metal-oxide-semiconductor (MOS) capacitors. A work function of 4.356 eV was determined for the Co-Si thin films via capacitance-voltage (C-Y) characterization which differs slightly from that extracted from ultraviolet photoemission spectroscopy (UPS) data (i.e., 4.8 eV). Simulation showed the difference between the C-V and UPS-derived data may be attributed to the existence of 8.3 x 10 (exponent 10) cm-2 interface charge density in the oxide-semiconductor junction. Poly-Si TFTs prepared using Si6 H12-based inks maintained the following electrical attributes: field effect mobility of 0.1 cm2V-1s-1; threshold voltage of 66 V; and, an on/off ratio of 1630. A BSIM3 version 3 NFET model was modified through global parametric extraction procedure to match the transfer characteristics of the fabricated poly-Si TFT. It is anticipated that this model can be utilized for future design simulation for solution-processed poly-Si circuits.

The ferroelectricity in fluorite-structure oxides such as hafnia and zirconia has attracted increasing interest since 2011. They have various advantages such as Si-based complementary metal oxide semiconductor-compatibility, matured deposition techniques, a low dielectric constant and the resulting decreased depolarization field, and stronger resistance to hydrogen annealing. However, the wake-up effect, imprint, and insufficient endurance are remaining reliability issues. Therefore, this paper reviews two major aspects: the advantages of fluorite-structure ferroelectrics for memory applications are reviewed from a material’s point of view, and the critical issues of wake-up effect and insufficient endurance are examined, and potential solutions are subsequently discussed.

Hf₁₋ₓZrₓO₂ (x ∼ 0.5–0.7) has been the leading candidate of ferroelectric materials with a fluorite crystal structure showing highly promising compatibility with complementary metal oxide semiconductor devices. Despite the notable improvement in device performance and processing techniques, the origin of its ferroelectric crystalline phase (space group: Pca2₁) formation has not been clearly elucidated. Several recent experimental and theoretical studies evidently showed that the interface and grain boundary energies of the higher symmetry phases (orthorhombic and tetragonal) contribute to the stabilization of the metastable non-centrosymmetric orthorhombic phase or tetragonal phase. However, there was a clear quantitative discrepancy between the theoretical expectation and experiment results, suggesting that the thermodynamic model may not provide the full explanation. This work, therefore, focuses on the phase transition kinetics during the cooling step after the crystallization annealing. It was found that the large activation barrier for the transition from the tetragonal/orthorhombic to the monoclinic phase, which is the stable phase at room temperature, suppresses the phase transition, and thus, plays a critical role in the emergence of ferroelectricity.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed. / Master of Science / According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

L’industrie microélectronique est régie depuis plusieurs années par la loi de miniaturisation. En particulier, en technologie CMOS, les procédés de fabrication de l’oxyde permettant l’isolation électrique entre les transistors nécessitent sans cesse d’être améliorés pour répondre aux défis de cette loi. Ainsi, on est passé du procédé d’isolation par oxydation localisée de silicium (LOCOS) au procédé d’isolation par tranchées (STI). Cependant, ce dernier a montré pour les technologies en développement des limitations liées au remplissage non parfait par la silice de tranchées de moins en moins larges (Voiding) et au ‘‘surpolissage’’ des zones les plus larges (Dishing). Le procédé FIPOS (full isolation by porous oxidation of silicon) a été donc proposé comme solution alternative. Il est basé sur la formation sélective et localisée du silicium poreux qui est transformé ensuite en silice par un recuit oxydant. Cette piste prometteuse a constitué le point de départ de ce travail. Dans ce contexte, la thèse s’est focalisée sur deux axes principaux qui concernaient d’une part la maîtrise du procédé d’anodisation électrochimique pour la formation du silicium poreux et d’autre part l’optimisation du procédé d’oxydation. Dans une première partie de notre travail, l’analyse des caractéristiques courant-tension I-V menée sur le silicium durant son anodisation électrochimique a permis de montrer que la formation du silicium poreux dépend fortement de la concentration en dopants. Cette propriété nous a permis de développer une technique simple d’extraction du profil de dopage dans le silicium de type p par voie électrochimique. On a montré que la résolution en profondeur de cette technique est liée au niveau du dopage et s’approche de celle du SIMS (spectroscopie de masse d'ions secondaires) pour les fortes concentrations avec une valeur estimée à 60 nm/décade. Dans une deuxième partie, nous avons mis en évidence la formation localisée du silicium poreux oxydé. En effet, un choix judicieux du potentiel d’anodisation permet de rendre poreux sélectivement des régions fortement dopées implantées sur un substrat de silicium faiblement dopé. Ces régions sont ensuite transformées en oxyde par un recuit oxydant. Par ailleurs, les conditions optimales des processus d’oxydation et d’anodisation permettant d’obtenir un oxyde final de bonne qualité diélectrique sont analysées. / The microelectronic industry is still ruled up to now by the law of miniaturization or scaling. In particular, in CMOS (complementary metal-oxide semiconductor) technology, the oxide allowing electric isolation between p- and n-MOS transistors has also been scaled down and has then exhibited different technological processes going from LOCOS (local oxidation of silicon) to STI (shallow trench isolation) and arriving to FIPOS (full isolation by porous oxidation of silicon). The latter seems to be the most promising alternative solution that can overcome actual limitations of voiding and dishing encountered in the STI process. The approach, which is based on selective formation of porous silicon and its easy transformation to silicon dioxide, has aroused our motivation to be well studied. In this context, the PhD project has first focused on the understanding of electrochemical porous silicon formation, and then on the study of porous silicon oxidation. In a first part of our work, we emphasize the dependence of porous silicon formation with the silicon doping concentration through the investigation of current-voltage I-V characteristics measured on p- and n-type silicon electrodes during electrochemical anodization. Taking advantage of this dependence, we have developed a very simple electrochemical method allowing an accurate determination of doping profiles in p-type silicon. It has been shown that the depth resolution of the technique is readily linked to the doping level and it approaches that of the secondary ion mass spectroscopy (SIMS) analysis for high doping concentrations with an estimated value of 60 nm/decade. In a second step, we highlight the selective formation of oxidized porous silicon. In fact, with a correct choice of the applied potential during anodization, only highly doped regions implanted on a lightly doped silicon wafer are preferentially turned into porous silicon and subsequently oxidized. Furthermore, we give the optimum conditions for oxidation and anodization processes which result in an insulating oxide of reliable dielectric properties.

Cette étude porte sur l’intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d’économies d’énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d’intégration. Cette thèse se propose d’employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l’oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc. / This study deals with the hybrid integration of Single Electron Transistors (SET) on a CMOS technology node. SET devices present high potentiels, particularly in terms of energy efficiency, but can't completely replace CMOS in electrical circuits. However, SETs and CMOS devices combination can solve this issue, opening the way toward very low operating power circuits, and high integration density. This thesis proposes itself to use for Back-End-Of-Line (BEOL) SETs realization, meaning in the oxide encapsulating CMOS, the nanodamascene fabrication process devised by C. Dubuc.

In this document, we present ou study about the conception and realization of VMOS and Schottky and JBS Diodes on Silicon Carbide. This work allowed us optimize and fabricate diodes using Tungsten as Schottky barrier on both Schottky and JBS diodes of different blocking capability between 1.2kV and 9kV. Moreover, our study of the VMOS, by considering the overall fabrication process, has permitted to identify the totality of the problems we are facing. Thusly we could ameliorate the devices and try new designs as the VIEMOS or the monolithic integration of temperature and current sensors.

La croissance continue et rapide du trafic de données dans les infrastructures de télécommunications, impose des niveaux de débit de transmission ainsi que de puissance de traitement de l’information, que les capacités intrinsèques des systèmes et microcircuits électroniques ne seront plus en mesure d’assurer à brève échéance : le développement de nouveaux scenarii technologiques s’avère indispensable pour répondre à la demande de bande passante imposée notamment par la révolution de l’internet, tout en préservant une consommation énergétique raisonnable. Dans ce contexte, l’intégration hétérogène fonctionnelle sur silicium de dispositifs photoniques à émission par la surface de type VCSEL utilisant des miroirs large-bandes ultra-compacts à cristaux photoniques constitue une stratégie prometteuse pour surmonter l’impasse technologique actuelle, tout en ouvrant la voie à un développement rapide d’architectures et de systèmes de communications innovants dans le cadre du mariage entre photonique et micro-nano-électronique. / The ever-growing demand for high-volume fast data transmission and processing is nowadays rapidly attaining the intrinsic limit of microelectronic circuits to offer high modulation bandwidth at reasonable power dissipation. Silicon photonics is set to break the technological deadlock aiming at a functional photonics-on-CMOS integration for innovative optoelectronic systems paving the way towards next-era communication architectures. Among the others photonic building blocks such as photodiodes, optical modulators and couplers, power-efficient compact semiconductors sources in the near-infrared telecommunication bands, characterized by performing modal features as well as thermal resiliency constitute an essential landmark to be achieved. Within such context, InP-based long-wavelength vertical-cavity surface-emitting lasers (VCSELs) using one-dimensional Si/SiO2 photonic crystals as wideband compact mirrors are proposed as next generation emitters for CMOS integration.

Les travaux présentés dans ce manuscrit sont axés sur le développement et la caractérisation de modules technologiques sur semiconducteurs à large bande interdite à base de nitrure de gallium (GaN), pour la réalisation de transistors et de cathodes froides. Ils ont été réalisés au sein du laboratoire III-V lab, commun aux entités : Alcatel - Thales - CEA Leti. Notre projet de recherche a bénéficié d'un soutien financier assuré par Thales Electron Devices (TED) et l'Agence Nationale de la Recherche ( ANR ). Concernant les transistors HEMT III-N, nos investigations se sont focalisées sur le développement des parties actives des transistors, incluant principalement la structuration des électrodes de grilles, l'étude de la passivation des grilles métalliques, ainsi que l'étude de diélectriques de grille pour la réalisation de structures MIS-HEMT.Les transistors MOS-HEMT « Normally-off » réalisés présentent des performances comparables à l'état de l'art, avec une densité de courant de drain maximum comprise entre 270 mA et 400 mA / mm, un ratio ION / IOFF > 1100, et des tensions de claquage > 200V. Les tensions de seuil sont comprises entre + 1,8 V et + 4 V. Nos contributions au développement des cathodes froides ont permis de démontrer une première émission dans le vide à partir de cathodes GaN, avec une densité de courant maximale de 300 µA / cm2 pour une tension de polarisation de 40 V / The results presented in this manuscript relate to technological developments and device processing on wide bandgap III-N semiconductor materials. They have been focused on III-N HEMT transistors and GaN cold cathodes. They have been realised within the III-V lab, which is a common entity between: Alcatel - Thales - CEA Leti. They have been financially supported by Thales Electron Devices company (TED) and the French National Research Agency ( ANR ). Regarding III-N HEMTs, our investigations have been focused on the development of device gate processing, which includes : the structuration of gate electrodes, the study of device passivation, and the realization of Metal-Insulator-Semiconductor High Mobility Electron Transistors ( MIS-HEMTs ). The “ Normally-off ” MOS-HEMT structures we have realized exhibit performances comparable to the state of the art, with a maximum drain current density between 270 and 400 mA / mm, a ION / IOFF ratio > 1.100, and a breakdown voltage > 200V. The threshold voltage values range between + 1,8 V and + 4V. We have also been able to demonstrate prototype GaN cold cathodes providing a maximum current density of 300 µA / cm2, emitted in vacuum for a bias voltage around 40 V