Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

The research conducted for this thesis seeks to understand issues associated with integrating a direct spread spectrum system (DSSS) transceiver on to a single chip. Various types of sequences, such as Kasami sequences and Gold sequences, are available for use in typical spread spectrum systems. For this thesis, complex spreading sequences (CSS) are used for improved cross-correlation and autocorrelation properties that can be achieved by using such a sequence. While CSS and DSSS are well represented in the existing body of knowledge, and discrete bulky hardware solutions exist – an effort to jointly integrate CSS and DSSS on-chip was identified to be lacking. For this thesis, spread spectrum architecture was implemented focussing on sub-systems that are specific to CSS. This will be the main contribution for this thesis, but the contribution is further appended by various RF design challenges: highspeed requirements make RF circuits sensitive to the effects of parasitics, including parasitic inductance, passive component modelling, as well as signal integrity issues. The integration is first considered more ideally, using mathematical sub-systems, and then later implemented practically using complementary metal-oxide semiconductor (CMOS) technology. The integration involves mixed-signal and radio frequency (RF) design techniques – and final integration involves several specialized analogue sub-systems, such as a class F power amplifier (PA), a low-noise amplifier (LNA), and LC voltage-controlled oscillators (VCOs). The research also considers various issues related to on-chip inductors, and also considers an active inductor implementation as an option for the VCO. With such an inductor a better quality factor is achievable. While some conventional sub-system design techniques are deployed, several modifications are made to adapt a given sub-system to the design requirements for this thesis. The contribution of the research lies in the circuit level modifications done at sub-system level aimed towards eventual integration. For multiple-access communication systems, where a number of independent users are required to share a common channel, the transceiver proposed in this thesis, can contribute towards improved data rate or bit error rate. The design is completed for fabrication in a standard 0.35-μm CMOS process with minimal external components. With an active chip area of about 5 mm2, the simulated transmitter consumes about 250 mW&the receiver consumes about 200 mW. AFRIKAANS : Die navorsing wat vir hierdie tesis onderneem is, beoog om kundigheid op te bou aangaande die kwessies wat met die integrasie van ‘n direkte spreispektrumstelsel (DSSS) sender-ontvanger op ‘n enkele skyfie verband hou. Verskeie tipes sekwensies, soos byvoorbeeld Kasami- en Gold-sekwensies, is vir gebruik in tipiese spreispektrumstelsels beskikbaar. Vir hierdie tesis is komplekse spreisekwensies (KSS) gebruik vir verbeterde kruis- en outokorrelasie-eienskappe wat bereik kan word deur so ‘n sekwensie te gebruik. Alhoewel DSSS en KSS reeds welbekend is, en diskrete hardeware oplossings reeds bestaan, is die vraag na gesamentlike geïntegreerde DSSS en KSS op een vlokkie geïdentifiseer. Vir hierdie tesis is spreispektrumargitektuur aangewend met die klem op KSS substelsels. Dit is dan ook die belangrikste bydrae van hierdie tesis, maar die bydrae gaan verder gepaard met verskeie RF-ontwerpuitdagings: hoëspoed-vereistes maak RF-stroombane sensitief vir die uitwerking van parasitiese komponente, met inbegrip van parasitiese induktansie, passiewe komponentmodellering en ook seinintegriteitskwessies. Die integrasie word eerstens meer idealisties oorweeg deur wiskundige substelsels te gebruik en dan later prakties te implementeer deur komplementêre metaaloksied-halfgeleiertegnologie (CMOS) te gebruik. Die integrasie behels gemengdesein- en radiofrekwensie(RF)-ontwerptegnieke – en finale integrasie behels verskeie gespesialiseerde analoë substelsels soos ‘n klas F-kragversterker (KV), ‘n laeruis-versterker (LRV), en LC-spanningbeheerde ossileerders (SBO’s). Die navorsing oorweeg ook verskeie kwessies in verband met op-skyfie induktors en oorweeg ook ‘n aktiewe induktorimplementering as ‘n opsie vir die SBO. Met sodanige induktor is ‘n beter kwaliteitsfaktor haalbaar. Hoewel enkele konvensionele substelsel-ontwerptegnieke aangewend word, word daar verskeie wysigings aangebring om ‘n gegewe substelsel by die ontwerpvereistes vir hierdie tesis aan te pas. Die bydrae van die navorsing is hoofsaaklik die stroombaanmodifikasies wat gedoen is op substelselvlak om integrasie te vergemaklik. Vir veelvoudige-toegang kommunikasiestelsels waar ‘n aantal onafhanklike gebruikers dieselfde seinkanaal moet deel, kan die sender-ontvanger voorgestel in hierdie tesis meewerk om die datatempo en fouttempo te verbeter. Die ontwerp is voltooi vir vervaardiging in ‘n standaard 0.35-μm CMOS-proses met minimale eksterne komponente. Met ‘n aktiewe skyfie-oppervlakte van ongeveer 5 mm2, verbruik die gesimuleerde sender ongeveer 250 mW en die ontvanger verbruik ongeveer 200 mW. / Thesis (PHD)--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

The field of infrared (IR) detector technology has shown vast improvements in terms of speed and performance over the years. Specifically the dynamic range (DR) and sensitivity of detectors showed significant improvements. The most commonly used technique of implementing these IR detectors is the use of charge-coupled devices (CCD). Recent developments show that the newly investigated bipolar complementary metal-oxide semiconductor (BiCMOS) devices in the field of detector technology are capable of producing similar quality detectors at a fraction of the cost. Prototyping is usually performed on low-cost silicon wafers. The band gap energy of silicon is 1.17 eV, which is too large for an electron to be released when radiation is received in the IR band. This means that silicon is not a viable material for detection in the IR band. Germanium exhibits a band gap energy of 0.66 eV, which makes it a better material for IR detection. This research is aimed at improving DR and sensitivity in IR detectors. CCD technology has shown that it exhibits good DR and sensitivity in the IR band. CMOS technology exhibits a reduction in prototyping cost which, together with electronic design automation software, makes this an avenue for IR detector prototyping. The focus of this research is firstly on understanding the theory behind the functionality and performance of IR detectors. Secondly, associated with this, is determining whether the performance of IR detectors can be improved by using silicon germanium (SiGe) BiCMOS technology instead of the CCD technology most commonly used. The Simulation Program with Integrated Circuit Emphasis (SPICE) was used to realise the IR detector in software. Four detectors were designed and prototyped using the 0.35 µm SiGe BiCMOS technology from ams AG as part of the experimental verification of the formulated hypothesis. Two different pixel structures were used in the four detectors, which is the silicon-only p-i-n diodes commonly found in literature and diode-connected SiGe heterojunction bipolar transistors (HBTs). These two categories can be subdivided into two more categories, which are the single-pixel-single-amplifier detectors and the multiple-pixel-single-amplifier detector. These were needed to assess the noise performance of different topologies. Noise influences both the DR and sensitivity of the detector. The results show a unique shift of the detecting band typically seen for silicon detectors to the IR band, accomplished by using the doping feature of HBTs using germanium. The shift in detecting band is from a peak of 250 nm to 665 nm. The detector still accumulates radiation in the visible band, but a significant portion of the near-IR band is also detected. This can be attributed to the reduced band gap energy that silicon with doped germanium exhibits. This, however, is not the optimum structure for IR detection. Future work that can be done based on this work is that the pixel structure can be optimised to move the detecting band even more into the IR region, and not just partially. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted

All DC/DC converter products include power electronic circuits for power conversion.It is important to find an efficient way for power conversion to reduce power losses and reduce the need for cooling and achieve environmentally friendly solutions.The use of semiconductor switches of wide band gap type is a solution to the problem.Therefore, the investigation of the SiC MOSFET in DC/DC converters is of crucial importance for the reduction of power losses.The thesis investigates the SiC MOSFET in three different tests.The efficiency test, the temperature test and the double pulse test.In the efficiency, the MOSFET STC3080KR and NTH4L022N120M3S are compared with their respective simulation made on PLECS.While in the temperature test the STC3080KR is investigated at different frequencies.In Double Pulse Test the MOSFET STC3080KR with 4-pin (TO-247 4L) package is compared with the MOSFET SCT3080KLHRC11 with 3-pin package (TO-247 N).The efficiency test shows that the MOSFET SCT3080KR in the practical test gives an efficiency in the range of 96,5-96,1% at 110kHz, 96-95,4% at 150kHz and 95,8-94,2% at 180kHz.While, the NTH4L022N120M3S gives an efficiency in the range of 98,1-97,1% at 110kHz, 96,3-96,2% at 150kHz and 96,1-95,5% at 180kHz.The efficiency given by the simulation is higher than the actual efficiency for both MOSFETs.However, the shape of the curves in the practical part matches the simulated one.The efficiency is not the same since the simulation do not consider all the losses present in the practical part.The temperature test shows that the temperature for the high side and low side increases when the frequency and the load current increases.However, some results show that when the load current increases at some point the low-side MOSFET will reach the temperature of the high-sided MOSFET and at the end it will exceed its value. This is due to the increment of the conduction losses since the low side MOSFET is basically the body diode incorporated in the MOSFET.Finally, the Double Pulse Test shows that the TO-247 N (3-pin) package switches with less source inductance compared to the TO-247 4L (4-pin) package.Therefore, the MOSFET SCT3080KLHRC11 (TO-247 N package) needs more time during the switching and which means that the switching power losses will be higher in comparison to the SCT3080KR as shown in Table 5.2 and Table 5.1. / Alla DC/DC-omvandlarprodukter inkluderar kraftelektroniska kretsar för effektomvandling. Detta gör att det är viktigt att hitta ett effektivt sätt för effektomvandlingen för att minska effektförlusterna och minska behovet av kylning och uppnå miljövänliga lösningar.Användningen av halvledaromkopplare med ett stort bandgap är en lösning på problemet.Därför är undersökningen av SiC MOSFET i DC/DC-omvandlare av avgörande betydelse för att minska effektförlusterna. Detta examensarbete undersöker SiC MOSFET i tre olika tester vilket är; Effektivitetstestet, temperaturen testet och double pulse testet.I effektivitets testet jämförs MOSFET STC3080KR och NTH4L022N120M3S med deras respektive simulering gjorda på PLECS.Medan i temperaturtestet undersöks STC3080KR vid olika frekvenser.I double pulse testet jämförs MOSFET STC3080KR med ett 4-stifts (TO-247 4L)-paket med MOSFET SCT3080KLHRC11 med ett 3-stiftspaket (TO-247 N).Effektivitetstestet visar att MOSFET SCT3080KR i det praktiska testet ger en verkningsgrad i intervallen 96,5-96,1% vid 110kHz, 96-95,4% vid 150kHz och 95,8-94,2% och vid 180kHz.Medan NTH4L022N120M3S visar en effektivitet i intervallet av 98,1-97,1% vid 110kHz, 96,3-96,2% vid 150kHz och 96,1-95,5% vid 180kHz.Verkningsgraden som ges av simuleringen är högre än den praktiska för båda MOSFET:erna.Formen på kurvorna i den praktiska delen matchar den simulerade.Verkningsgraden är inte densamma eftersom simuleringen inte tar hänsyn till alla förluster som finns i den praktiska delen.Temperaturtestet visar att temperaturen för den höga sidan och lågsidan ökar när frekvensen och belastningsströmmen ökar.Vissa resultat visar att när belastningsströmmen ökar lågsidans MOSFET når temperaturen hos den högsidiga MOSFET:en och i slutet kommer den att överstiga dess värde.Detta beror på ökningen av ledningsförlusterna eftersom MOSFET på lågsidan i grunden är kroppsdioden som ingår i MOSFET.Slutligen, visar double pulse testet att TO-247 N (3-stifts)-paketet växlar med mindre källinduktans jämfört med till TO-247 4L (4-stifts)-paketet.Därför behöver MOSFET SCT3080KLHRC11 (TO-247 N-paket) mer tid under växlingen och därför blir växlingseffektförlusterna högre jämfört med SCT3080KR, detta visas i Tabell 5.2 och Tabell 5.1.

科学研究費補助金 研究種目:基盤研究(A)(2) 課題番号:13305005 研究代表者:近藤 博基 研究期間:2001-2004年度

Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher. / Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre. / <p>QC 20170524</p>

Diese Arbeit beschäftigt sich mit der „First-Principles“ atomskaligen Modellierung der HfO2-basierten high-k-Gate-Isolatorschichten der Metalloxid-Halbleiter-Feldeffekttransistoren. Die theoretischen Untersuchungen basieren auf Dichtefunktionaltheorie und Nichtgleichgewicht-Greensche-Funktion-Formalismen. Eine der wichtigsten Eigenschaften eines Gate-Isolators ist der Wert seiner Bandlücke. Die Bandlücke eines gemischten Festkörpers aus SiO2 und ZrO2 oder HfO2 wird auf der Grundlage der „Generalized Quasi-Chemical“ Approximation in Kombination mit dem „Cluster Expansion“ Ansatz berechnet. Zu diesem Zweck wurde Dichtefunktionaltheorie für die Berechnung der Eigenschaften verschiedener Konfigurationen möglicher Elementarzellen durchgeführt. Es wurde ein fast linearer Verlauf für die Bandlücke eines aus SiO2 und HfO2 gemischten Festkörpers berechnet. Im Vergleich zu dem üblichen SiO2 Gate-Isolator, haben die high-k-Gate-Isolatoren eine höhere Defektdichte, die hauptsächlich aus Sauerstoffleerstellen bestehen. Dies führt zu mehreren Problemen, wie zum Beispiel höherer Leckstrom, Schwellenspannungsverschiebung und Degradation des Gateoxids. Daher wurde eine umfassende Untersuchung der verschiedenen Eigenschaften von Sauerstofffehlstellen in HfO2 durchgeführt, indem wichtige Parameter wie zum Beispiel die Formationsenergien und die Lage der Defektniveaus in der Bandlücke berechnet wurden. Es wurde durch die theoretischen Berechnungen gezeigt, dass die schädlichen Auswirkungen von Sauerstofffehlstellen durch die Einführung von Lanthan-Atomen in dem HfO2 Kristallgitter teilweise zu verringern sind. Energetisch gesehen bevorzugen die Lanthan-Atome die Hf-Gitterplätze in der Nachbarschaft einer Sauerstofffehlstelle und führen dadurch zu der Passivierung durch Sauerstoffleerstelle induzierten Defektniveaus. Die high-k-Isolatorschicht in den heutigen Transistoren besteht aus drei Schichten: einem Metallgate, einer HfO2-Schicht als Haupt-Gate-Isolator und einer sehr dünnen SiO2 Übergangsschicht zwischen Gateoxid und Si. Die Einführung eines Metallgates führt zu einigen Problemen bei der Einstellung einer geeigneten Schwellenspannung in den Transistoren. Theoretische Berechnungen in einer komplexen Modellstruktur von der Si/SiO2/HfO2-Grenzfläche zeigen, dass die dotierten Lanthan-Atome energetisch die SiO2/HfO2-Grenzfläche bevorzugen, was wiederum ein Dipolmoment an der Grenzfläche erzeugt. Dieses Dipolmoment kann verwendet werden, um die richtige Schwellenspannung wieder einzustellen. Schließlich wird in den experimentellen Messungen festgestelltes progressives Degradationsverhalten von high-k-Gate-Isolatoren mit einem theoretischen Modell erklärt. Dieses Modell basiert auf ab-initio-Berechnungen und zeigt, wie die Erzeugung geladener Sauerstoffleerstellen und deren Migration unter der angelegten Gatespannung zu einer progressiven Erhöhung des Leckstroms und folglich zu einer Degradation der Isolatorschicht führt.:List of Figures 7 List of Tables 9 List of Symbols 10 List of Abbreviations 11 Chapter 1: Introduction 12 Chapter 2: Theory of Atomic-Scale First-Principles Calculations 15 2.1 Theoretical methods 15 2.2 Density functional theory 17 2.3 Non-equilibrium Green’s function formalism 23 Chapter 3: Calculations for Bulk High-k Materials 27 3.1 Bulk high-k materials 27 3.2 Crystalline insulators 27 3.3 Solid solutions 29 3.3.1 Cluster expansion approach 30 3.3.2 Band gap and bowing parameter 33 3.3.3 Calculation of internal stress 40 3.4 Leakage current 41 Chapter 4: Defects in Bulk High-k Materials 43 4.1 Defects in high-k gate dielectrics 43 4.2 Oxygen vacancies in monoclinic HfO2 44 4.2.1 Neutral oxygen vacancies 44 4.2.2 Charged oxygen vacancies 46 4.3 Hybrid functional 50 4.4 Double oxygen vacancies 56 4.5 Interaction of oxygen vacancies with La-doping 61 4.5.1 La doping in m-HfO2 61 4.5.2 Complex LaHfVO defects 64 Chapter 5: Interface Properties of High-k Gate Stack 72 5.1 high-k gate-stack 72 5.1.1 Atomic-scale model structure for a high-k gate-stack 72 5.1.2 Electronic structure 74 5.1.3 Leakage current 76 5.2 Band offset 80 5.3 Threshold voltage engineering with La doping 84 Chapter 6: Degradation of the High-k Gate Stack 90 6.1 Reliability issues in high-k gate-stack 90 6.2 Calculations and experimental methods 91 6.3 Leakage current 92 6.4 Defect generation 100 6.5 Explaining progressive SILC in high-k dielectrics 102 Chapter 7: Conclusions 104 Bibliography 106 Selbständigkeitserklärung 119 Danksagung 120 Lebenslauf 121 Veröffentlichungen 122 / This thesis deals with the first-principles atomic-scale modeling of the HfO2-based high-k gate-insulator layer of the metal-oxide-semiconductor field-effect transistors. The theoretical investigations are based on density functional theory and non-equilibrium Green's function formalisms. One of the important properties of the gate insulator is the value of its band gap. The band gap of amorphous solid mixtures of SiO2 and ZrO2 or HfO2 is calculated based on generalized quasi-chemical approximation combined with a cluster expansion approach, by performing density functional calculations on different configurations of possible unit cells. An almost linear variation of the band gap is obtained for solid mixtures of SiO2 and HfO2. One drawback of the high-k gate-insulator, comparing to the standard SiO2, is high density of defects, particularly oxygen vacancies, which leads to several problems such as enhancement of the leakage current, threshold voltage instability, and degradation of the gate-oxide. A comprehensive investigation of different properties of oxygen vacancies in HfO2 is conducted by the calculation of formation energies and induced trap levels. It is shown based on theoretical calculations that the harmful effects of oxygen vacancies can be partially healed by introducing lanthanum atoms into the defected HfO2 crystal. Lanthanum atoms energetically prefer to occupy Hf lattice sites close to the oxygen vacancies and passivate the induced defect levels. The state-of-the-art high-k gate-stacks consist of a metal-gate on a HfO2 layer, as the main part of the gate insulator, and a very thin SiO2 intermediate layer between high-k material and Si. The introduction of a metal-gate raises some problem in the adjustment of an appropriate threshold voltage. Theoretical calculations in a complex model structure of the Si/SiO2/HfO2 interface reveals that the lanthanum atoms energetically prefer to stay at the SiO2/HfO2 interface, which in turn results in a dipole moment. This dipole moment can be employed to adjust the threshold voltage in high-k/metal-gate stacks. Finally, a theoretical model, which can quiet well explain the experimental measurements, is introduced for the progressive degradation of the high-k gate-insulators. This model is based on ab-initio calculations and shows how the generation of charged vacancies and their migration under the applied gate voltage leads to the progressive enhancement of the leakage current and consequently to the degradation of the insulator layer.:List of Figures 7 List of Tables 9 List of Symbols 10 List of Abbreviations 11 Chapter 1: Introduction 12 Chapter 2: Theory of Atomic-Scale First-Principles Calculations 15 2.1 Theoretical methods 15 2.2 Density functional theory 17 2.3 Non-equilibrium Green’s function formalism 23 Chapter 3: Calculations for Bulk High-k Materials 27 3.1 Bulk high-k materials 27 3.2 Crystalline insulators 27 3.3 Solid solutions 29 3.3.1 Cluster expansion approach 30 3.3.2 Band gap and bowing parameter 33 3.3.3 Calculation of internal stress 40 3.4 Leakage current 41 Chapter 4: Defects in Bulk High-k Materials 43 4.1 Defects in high-k gate dielectrics 43 4.2 Oxygen vacancies in monoclinic HfO2 44 4.2.1 Neutral oxygen vacancies 44 4.2.2 Charged oxygen vacancies 46 4.3 Hybrid functional 50 4.4 Double oxygen vacancies 56 4.5 Interaction of oxygen vacancies with La-doping 61 4.5.1 La doping in m-HfO2 61 4.5.2 Complex LaHfVO defects 64 Chapter 5: Interface Properties of High-k Gate Stack 72 5.1 high-k gate-stack 72 5.1.1 Atomic-scale model structure for a high-k gate-stack 72 5.1.2 Electronic structure 74 5.1.3 Leakage current 76 5.2 Band offset 80 5.3 Threshold voltage engineering with La doping 84 Chapter 6: Degradation of the High-k Gate Stack 90 6.1 Reliability issues in high-k gate-stack 90 6.2 Calculations and experimental methods 91 6.3 Leakage current 92 6.4 Defect generation 100 6.5 Explaining progressive SILC in high-k dielectrics 102 Chapter 7: Conclusions 104 Bibliography 106 Selbständigkeitserklärung 119 Danksagung 120 Lebenslauf 121 Veröffentlichungen 122

Les procédés bipolaires semi-conducteurs complémentaires à oxyde de métal (BiCMOS) peuvent être considérés comme étant la solution la plus généralepour les produits RF car ils combinent la fabrication sophistiquée du CMOSavec la vitesse et les capacités de conduction des transistors bipolaires silicium germanium(SiGe) à hétérojonction (HBT). Les HBTs, réciproquement, sontles principaux concurrents pour combler partiellement l'écart de térahertzqui décrit la plage dans laquelle les fréquences générées par les transistors etles lasers ne se chevauchent pas (environ 0.3 THz à 30 THz). A_n d'évaluerles capacités de ces dispositifs futurs, une méthodologie de prévision fiable estsouhaitable. L'utilisation d'un ensemble hétérogène d'outils et de méthodes desimulations permet d'atteindre successivement cet objectif et est avantageusepour la résolution des problèmes. Plusieurs domaines scientifiques sont combinés, tel que la technologie de conception assistée par ordinateur (TCAO),la modélisation compacte et l'extraction des paramètres.Afin de créer une base pour l'environnement de simulation et d'améliorerla confirmabilité pour les lecteurs, les modèles de matériaux utilisés pour lesapproches hydrodynamiques et de diffusion par conduction sont introduits dèsle début de la thèse. Les modèles physiques sont principalement fondés surdes données de la littérature basées sur simulations Monte Carlo (MC) ou dessimulations déterministes de l'équation de transport de Boltzmann (BTE).Néanmoins, le module de TCAO doit être aussi étalonné sur les données demesure pour une prévision fiable des performances des HBTs. L'approchecorrespondante d'étalonnage est basée sur les mesures d'une technologie depointe de HBT SiGe pour laquelle un ensemble de paramètres spécifiques àla technologie du modèle compact HICUM/L2 est extrait pour les versionsdu transistor à haute vitesse, moyenne et haute tension. En s'aidant de cesrésultats, les caractéristiques du transistor unidimensionnel qui sont généréesservent de référence pour le profil de dopage et l'étalonnage du modèle. Enélaborant des comparaisons entre les données de références basées sur les mesureset les simulations, la thèse fait progresser l'état actuel des prévisionsbasées sur la technologie CAO et démontre la faisabilité de l'approche.Enfin, une technologie future de 28nm performante est prédite en appliquantla méthodologie hétérogène. Sur la base des résultats de TCAO, leslimites de la technologie sont soulignées. / Bipolar complementary metal-oxide-semiconductor (BiCMOS) processescan be considered as the most general solution for RF products, as theycombine the mature manufacturing tools of CMOS with the speed and drivecapabilities of silicon-germanium (SiGe) heterojunction bipolar transistors(HBTs). HBTs in turn are major contenders for partially filling the terahertzgap, which describes the range in which the frequencies generated bytransistors and lasers do not overlap (approximately 0.3THz to 30 THz). Toevaluate the capabilities of such future devices, a reliable prediction methodologyis desirable. Using a heterogeneous set of simulation tools and approachesallows to achieve this goal successively and is beneficial for troubleshooting.Various scientific fields are combined, such as technology computer-aided design(TCAD), compact modeling and parameter extraction.To create a foundation for the simulation environment and to ensure reproducibility,the used material models of the hydrodynamic and drift-diffusionapproaches are introduced in the beginning of this thesis. The physical modelsare mainly based on literature data of Monte Carlo (MC) or deterministicsimulations of the Boltzmann transport equation (BTE). However, the TCADdeck must be calibrated on measurement data too for a reliable performanceprediction of HBTs. The corresponding calibration approach is based onmeasurements of an advanced SiGe HBT technology for which a technology specific parameter set of the HICUM/L2 compact model is extracted for thehigh-speed, medium-voltage and high-voltage transistor versions. With thehelp of the results, one-dimensional transistor characteristics are generatedthat serve as reference for the doping profile and model calibration. By performingelaborate comparisons between measurement-based reference dataand simulations, the thesis advances the state-of-the-art of TCAD-based predictionsand proofs the feasibility of the approach.Finally, the performance of a future technology in 28nm is predicted byapplying the heterogeneous methodology. On the basis of the TCAD results,bottlenecks of the technology are identified. / Bipolare komplementäre Metall-Oxid-Halbleiter (BiCMOS) Prozesse bietenhervorragende Rahmenbedingungen um Hochfrequenzanwendungen zurealisieren, da sie die fortschrittliche Fertigungstechnik von CMOS mit derGeschwindigkeit und Treiberleistung von Silizium-Germanium (SiGe) Heterostruktur-Bipolartransistoren (HBTs) verknüpfen. Zudem sind HBTs bedeutendeWettbewerber für die teilweise Überbrückung der Terahertz-Lücke, derFrequenzbereich zwischen Transistoren (< 0.3 THz) und Lasern (> 30 THz).Um die Leistungsfähigkeit solcher zukünftigen Bauelemente zu bewerten, isteine zuverlässige Methodologie zur Vorhersage notwendig. Die Verwendungeiner heterogenen Zusammenstellung von Simulationstools und Lösungsansätzenerlaubt es dieses Ziel schrittweise zu erreichen und erleichtert die Fehler-_ndung. Verschiedene wissenschaftliche Bereiche werden kombiniert, wie zumBeispiel der rechnergestützte Entwurf für Technologie (TCAD), die Kompaktmodellierungund Parameterextraktion.Die verwendeten Modelle des hydrodynamischen Simulationsansatzes werdenzu Beginn der Arbeit vorgestellt, um die Simulationseinstellung zu erläuternund somit die Nachvollziehbarkeit für den Leser zu verbessern. Die physikalischenModelle basieren hauptsächlich auf Literaturdaten von Monte Carlo(MC) oder deterministischen Simulationen der Boltzmann-Transportgleichung(BTE). Für eine zuverlässige Vorhersage der Eigenschaften von HBTs muss dieTCAD Kon_guration jedoch zusätzlich auf der Grundlage von Messdaten kalibriertwerden. Der zugehörige Ansatz zur Kalibrierung beruht auf Messungeneiner fortschrittlichen SiGe HBT Technologie, für welche ein technologiespezifischer HICUM/L2 Parametersatz für die high-speed, medium-voltage undhigh-voltage Transistoren extrahiert wird. Mit diesen Ergebnissen werden eindimensionaleTransistorcharakteristiken generiert, die als Referenzdaten fürdie Kalibrierung von Dotierungspro_len und physikalischer Modelle genutztwerden. Der ausführliche Vergleich dieser Referenz- und Messdaten mit Simulationengeht über den Stand der Technik TCAD-basierender Vorhersagenhinaus und weist die Machbarkeit des heterogenen Ansatzes nach.Schlieÿlich wird die Leistungsfähigkeit einer zukünftigen Technologie in28nm unter Anwendung der heterogenen Methodik vorhergesagt. Anhand derTCAD Ergebnisse wird auf Engpässe der Technologie hingewiesen.