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M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology, / “If we think oil is a problem now, just wait 20 years. It’ll be a nightmare.” — Jeremy Rifkin, Foundation of Economic Trends, Washington, D.C., August 2003. This statement harmonises with the reality that human civilisation faces today. As a result, humankind has been forced to look for alternatives to fossil fuels. Among possible solutions, fuel cell (FC) technology has received a lot of attention because of its potential to generate clean energy. Fuel cells have the advantage that they can be used in remote telecommunication sites with no grid connectivity as the majority of telecommunication equipment operates from a DC voltage supply. Power plants based on phosphoric acid fuel cell (PAFC) have been installed worldwide supplying urban areas, shopping centres and medical facilities with electricity, heat and hot water. Although these are facts regarding large scale power plants for on-site use, portable units have been explored as well. Like any other fuel cell, the PAFC output power is highly unregulated leading to a drastic drop in the output voltage with changing load value. Therefore, various DC–DC converter topologies with a wide range of input voltages can be used to regulate the fuel cell voltage to a required DC load. An interleaved synchronous buck converter intended for efficiently stepping down the energy generated by a PAFC was designed and developed. The design is based on the National Semiconductor LM5119 IC. A LM5119 evaluation board was redesigned to meet the requirements for the application. The measurements were performed and it was found that the converter achieved the expectations. The results showed that the converter efficiently stepped down a wide range of input voltages (22 to 46 V) to a regulated 13.8 V while achieving a 93 percent efficiency. The conclusions reached and recommendations for future research are presented. / Telkom Centre of Excellence, TFMC, M-Tech, THRIP.

This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined. / text

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application. The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range. The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance. / Master of Science

The role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, today's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses to a minimum. The power conversion circuitry in a system is a very good place to reduce a large amount of unnecessary loss. This can be done using circuit topologies that are low loss in nature. For low loss and high performance, soft switching topologies have offered solutions in some cases. Also, limited study has been performed on device aging effects on switching mode power converting circuits. The impact of this effect on a converter's overall efficiency is theoretically known but with little experimental evidence in support. In this thesis, non-isolated buck type switching converters will be the main focus. This type of power conversion is widely used in many systems for DC to DC voltage step down. Newer methods and topologies to raise converter power efficiency are discussed, including a new synchronous ZVT topology . Also, a study has been performed on device aging effects on converter efficiency. Various scenarios of voltage conversion, switching frequency, and circuit components as well as other conditions have been considered. Experimental testing has been performed in both cases, ZVT's benefits and device aging effects, the results of which are discussed as well.

In order to provide the means to set up a control theory lab experiment involving position control of a brushed DC motor with current feedback, a pulse-width modulated motor controller was designed. The output voltage is controlled by an analog reference signal and the magnitude of the output current and voltage are measured and output. These inputs and outputs are connected to a DAQ I/O-unit such that the lab experiment can be implemented digitally. In addition, defining equations for the whole system were derived. Comparison between measurements and model showed it possible to use the current as feedback if low-pass filtered and the angular displacement controlled over a small angular interval.

All DC/DC converter products include power electronic circuits for power conversion.It is important to find an efficient way for power conversion to reduce power losses and reduce the need for cooling and achieve environmentally friendly solutions.The use of semiconductor switches of wide band gap type is a solution to the problem.Therefore, the investigation of the SiC MOSFET in DC/DC converters is of crucial importance for the reduction of power losses.The thesis investigates the SiC MOSFET in three different tests.The efficiency test, the temperature test and the double pulse test.In the efficiency, the MOSFET STC3080KR and NTH4L022N120M3S are compared with their respective simulation made on PLECS.While in the temperature test the STC3080KR is investigated at different frequencies.In Double Pulse Test the MOSFET STC3080KR with 4-pin (TO-247 4L) package is compared with the MOSFET SCT3080KLHRC11 with 3-pin package (TO-247 N).The efficiency test shows that the MOSFET SCT3080KR in the practical test gives an efficiency in the range of 96,5-96,1% at 110kHz, 96-95,4% at 150kHz and 95,8-94,2% at 180kHz.While, the NTH4L022N120M3S gives an efficiency in the range of 98,1-97,1% at 110kHz, 96,3-96,2% at 150kHz and 96,1-95,5% at 180kHz.The efficiency given by the simulation is higher than the actual efficiency for both MOSFETs.However, the shape of the curves in the practical part matches the simulated one.The efficiency is not the same since the simulation do not consider all the losses present in the practical part.The temperature test shows that the temperature for the high side and low side increases when the frequency and the load current increases.However, some results show that when the load current increases at some point the low-side MOSFET will reach the temperature of the high-sided MOSFET and at the end it will exceed its value. This is due to the increment of the conduction losses since the low side MOSFET is basically the body diode incorporated in the MOSFET.Finally, the Double Pulse Test shows that the TO-247 N (3-pin) package switches with less source inductance compared to the TO-247 4L (4-pin) package.Therefore, the MOSFET SCT3080KLHRC11 (TO-247 N package) needs more time during the switching and which means that the switching power losses will be higher in comparison to the SCT3080KR as shown in Table 5.2 and Table 5.1. / Alla DC/DC-omvandlarprodukter inkluderar kraftelektroniska kretsar för effektomvandling. Detta gör att det är viktigt att hitta ett effektivt sätt för effektomvandlingen för att minska effektförlusterna och minska behovet av kylning och uppnå miljövänliga lösningar.Användningen av halvledaromkopplare med ett stort bandgap är en lösning på problemet.Därför är undersökningen av SiC MOSFET i DC/DC-omvandlare av avgörande betydelse för att minska effektförlusterna. Detta examensarbete undersöker SiC MOSFET i tre olika tester vilket är; Effektivitetstestet, temperaturen testet och double pulse testet.I effektivitets testet jämförs MOSFET STC3080KR och NTH4L022N120M3S med deras respektive simulering gjorda på PLECS.Medan i temperaturtestet undersöks STC3080KR vid olika frekvenser.I double pulse testet jämförs MOSFET STC3080KR med ett 4-stifts (TO-247 4L)-paket med MOSFET SCT3080KLHRC11 med ett 3-stiftspaket (TO-247 N).Effektivitetstestet visar att MOSFET SCT3080KR i det praktiska testet ger en verkningsgrad i intervallen 96,5-96,1% vid 110kHz, 96-95,4% vid 150kHz och 95,8-94,2% och vid 180kHz.Medan NTH4L022N120M3S visar en effektivitet i intervallet av 98,1-97,1% vid 110kHz, 96,3-96,2% vid 150kHz och 96,1-95,5% vid 180kHz.Verkningsgraden som ges av simuleringen är högre än den praktiska för båda MOSFET:erna.Formen på kurvorna i den praktiska delen matchar den simulerade.Verkningsgraden är inte densamma eftersom simuleringen inte tar hänsyn till alla förluster som finns i den praktiska delen.Temperaturtestet visar att temperaturen för den höga sidan och lågsidan ökar när frekvensen och belastningsströmmen ökar.Vissa resultat visar att när belastningsströmmen ökar lågsidans MOSFET når temperaturen hos den högsidiga MOSFET:en och i slutet kommer den att överstiga dess värde.Detta beror på ökningen av ledningsförlusterna eftersom MOSFET på lågsidan i grunden är kroppsdioden som ingår i MOSFET.Slutligen, visar double pulse testet att TO-247 N (3-stifts)-paketet växlar med mindre källinduktans jämfört med till TO-247 4L (4-stifts)-paketet.Därför behöver MOSFET SCT3080KLHRC11 (TO-247 N-paket) mer tid under växlingen och därför blir växlingseffektförlusterna högre jämfört med SCT3080KR, detta visas i Tabell 5.2 och Tabell 5.1.