Distributed Series Reactors (DSRs) can be used to control power flow to more fully utilize the capacity of a transmission network, delaying investment in new transmission lines. In this study the IEEE 39 bus standard test system is modified to a 3-phase, unbalanced model consisting of 230 kV, 345 kV and 500 kV lines, where lines of different voltage run in parallel. This model is used to study load growth and the effect of adding DSRs to alleviate resulting overloads, and in particular to alleviate overloads on lines of different voltage running in parallel. The economic benefit of adding DSRs to the network is compared to the addition of new transmission lines in the network. In the second part of the work, the effect of unsymmetrical operation of DSRs on a single transmission line is studied and compared to the symmetrical operation of DSRs. It is found that the unsymmetrical operation of DSRs is more economical. Finally the unsymmetrical operation of DSRs to reduce voltage imbalance in the network is considered. / Master of Science

No description available.

The electric power system is undergoing a paradigm change on how electric energy is generated, transmitted, and delivered. Power electronics systems which can provide medium-voltage (MV) to high-voltage (HV) output (>13.8 kV ac, > 20 kV dc) with much faster dynamic response (> 10 kHz bandwidth) or high switching-frequency will enable new electronic energy network architectures, like MVDC power delivery, underground solid-state power substation (SSPS), and high-density power electronics building block (PEBB); help drive the levelized cost of electricity (LCOE) of renewable energy on par with conventional power generation; deliver precise and clean power to loads like high-speed electric motors; push the future power system toward 100% renewable energy and energy storage supplied. In the MV to HV area, the power conversion solution is dominated by silicon devices, like SCR, IGCT, and IGBT, which are slow in nature, posing significant switching losses and bulky auxiliary components like turn-on snubbers. Devices in series are required to reach higher voltage. High-frequency HV converter in two-level or three-level bridges running 20 kHz or higher in many emerging applications, like MVDC networks with high-frequency transformers and energy storage integration is hard to be built by silicon solutions. The emerging HV wide-bandgap (WBG) power semiconductors, e.g., 10 kV SiC MOSFETs offer higher blocking capability, faster and more efficient switching performances. This makes the high-frequency power conversion technology feasible for the MV area. To build a MV high-frequency power converter with high-power density, 10 kV SiC MOSFETs in series are required to reach >10 kV operation dc voltage as the single device rating is still limited by the semiconductor process and packaging capability. However, the knowledge of dynamic voltage sharing of high-speed HV SiC devices under high dv/dt rate and effective balancing methods are not fully explored. Both the voltage imbalance and the robust device voltage balancing control are not studied clearly in the existing literature. This dissertation evaluates the voltage imbalance of series-connected 10 kV SiC MOSFETs thoroughly. The parasitic capacitors connected with device terminals are found to be a unique factor for the voltage imbalance of series-connected SiC MOSFETs, which have a significant impact on the dv/dt of different devices based on the detailed analysis. The unbalanced dv/dt and the gate signal mismatch together result in the voltage imbalance of series-connected SiC MOSFETs and a set of new voltage balancing control methods are proposed. Passive capacitor compensation and closed-loop short pulse gate signal control are proposed to solve the voltage imbalance caused by the unbalanced dv/dt. Closed-loop gate delay time control is proposed to solve the voltage imbalance caused by the gate signal mismatch. Two gate driver prototypes are designed and verified for the proposed voltage balancing control methods. As the number of devices increases, the voltage balancing methods under the device-level will be complex and risky to coordinate. Therefore, the converter-level device voltage balancing methods are desired when over three devices are in stack. Therefore, this dissertation proposes to use the 3-level (3L) neutral-point-clamped (NPC) converter structure as a converter-level approach to simplify the voltage balancing control of series-connected SiC MOSFETs. A new modulation strategy is proposed to control the loss of clamping diodes, so compact MV SiC Schottky diodes can be selected to reduce the impact of extra components on the power density. Compared to the phase-leg with direct series-connected SiC MOSFETs, the phase-leg designed with the converter-level approach achieves similar power density, easier voltage balancing control, and better efficiency, which is attractive for both two and four devices in series connection. Finally, this dissertation studies the impact of series-connected 10 kV SiC MOSFETs on MV phase-leg volume reduction with the example of multi-level flying capacitor (FC) converters. The relation between the capacitances of FCs and the device voltage is studied and a new design procedure for FCs is developed to achieve minimum FC energy and regulate the maximum device voltage. With the design procedure, the total FC volumes of a 22 kV 5-level FC converter and a 22 kV 3-level FC converter with series-connected 10 kV SiC MOSFETs are calculated and compared. Series-connected 10 kV SiC MOSFETs are found to help significantly reduce the total FC volume (> 85 %). In summary, this dissertation demonstrates that the direct series connection of 10 kV SiC MOSFETs is a reliable solution for the MV converter design, and the converter-level approach is a better voltage balancing control method. This dissertation also presents a quantitative analysis of the volume reduction enabled by the series-connected 10 kV SiC MOSFETs in MV converter phase-leg design. / Doctor of Philosophy / Emerging industrial applications require medium voltage (MV) power converters. For existing MV converter solutions with Si IGBT, complex system structures are usually required, which affects the efficiency, power density, and cost of the system. For the design of MV converter, the recent 10 kV SiC MOSFET has the promising potential to improve efficiency and power density by adopting a simpler topology and fewer conversion stages. New design challenges also emerge with the new 10 kV SiC MOSFETs and one of them is the device voltage control during the operation. This dissertation mainly focuses on the voltage balancing control of series-connected 10 SiC MOSFETs, which is an attractive solution to build the MV converter phase-leg in a simple structure. Several voltage balance control methods are proposed and compared in this dissertation, which helps justify that the series-connected SiC MOSFET is a reliable approach for the MV converter design. In addition, this dissertation also analyzes the volume reduction enabled by the series-connected SiC MOSFETs with the example of a multi-level flying capacitor converter in dc-ac applications.

This dissertation presents voltage stabilization techniques for flying capacitors used in soft-switching multilevel active power filters. The proposed active filter has proved to be a solution for power system harmonics produced by static high power converters. However, voltage unbalance of the clamping capacitors in the active filter in practical applications was observed due to its unequal parameters. Thus, the fundamentals of flying capacitors were characterized dealing with voltage balancing between flying capacitors and dc capacitors under practical operation, rather than ideal conditions. The study of voltage balancing provides the fundamental high-level solutions to flying capacitor based multilevel converter and inverter applications without additional passive balancing circuits. The use of proposed voltage balancing techniques made it possible to have a simple structure for solving the problems associated with the conventional bulky passive resistors and capacitor banks. Furthermore, the proposed control algorithms can be implemented with a real time digital signal processor. It can achieve the high performance of the active filter by compensating an adaptive gain to the controller. The effectiveness of the proposed controller was confirmed through various simulations and experiments. The focus of this study is to identify and develop voltage stabilization techniques for flying capacitors used in a proposed active filter. The voltage unbalance is investigated and characterized to provide safe operations. After having defined the problems associated with the voltage unbalance, the most important voltage stabilization techniques are proposed to solve this problem, in conjunction with an instantaneous reactive power (IRP) control of an active filter. In order to reduce the switching losses and improve the efficiency of the active filter, the proposed soft-switching techniques were evaluated through simulation and experimentation. Experimental results indicate that the proposed active filter achieved zero-voltage conditions in all of the main switches and zero-current turn-off conditions to the auxiliary switches during commutation processes. Also, various studies on soft-switching techniques, multilevel inverters, control issues and dynamics of the proposed active filter are discussed and analyzed in depth. / Ph. D.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / This work proposes the use of an auxiliary circuit to perform the voltage balancing and reduce the low frequency currents of the DC Bus center point of a three-phase transformerless UPS. The Bus voltage unbalance may occur due to the connection of unbalanced loads and non-idealities of the circuit and may impair the quality of the UPS output voltage. The low frequency current components occur due to the connection of non-linear or unbalanced loads. With the occurrence of these currents, there is an increase in the DC Bus voltage ripple, making it necessary to use a DC Bus with significant capacitance values. Moreover, these currents should increase the losses in the capacitor and deteriorate its lifespan. Thus, it is proposed the use of an auxiliary circuit comprising a switching branch and an inductor, whose function is to reduce the harmonic content from the currents flowing through the central point of the capacitive divider, in addition to ensuring the balancing of the DC Bus voltages. It is carried out the design of a three-phase transformerless UPS and the proposed auxiliary circuit, besides the design of its control systems. Simulation and experimental results demonstrate the procedures developed over this work and validate the functionality of the proposed circuit with respect to its purpose. / Este trabalho propõe a utilização de um circuito auxiliar para realizar o equilíbrio de tensão e redução das correntes de baixa frequência do ponto central do barramento CC de uma UPS trifásica sem transformador. O desequilíbrio de tensão do barramento pode ocorrer devido a conexão de cargas desequilibradas e não-idealidades do circuito e podem prejudicar a qualidade da tensão de saída da UPS. Já as componentes de corrente em baixa frequência ocorrem devido à conexão de cargas não-lineares ou desequilibradas. Com a ocorrência dessas correntes, há um aumento na ondulação de tensão do barramento CC, tornando necessário a utilização de expressivos valores de capacitância. Além disso essas correntes devem aumentar as perdas nos capacitores e deteriorar sua vida útil. Dessa forma, propõe-se a utilização de um circuito auxiliar composto por um braço de interruptores e um indutor, cuja função é reduzir o conteúdo harmônico proveniente das correntes que circulam pelo ponto central do divisor capacitivo, além de assegurar o equilíbrio das tensões do barramento CC. É realizado o dimensionamento de uma UPS trifásica sem transformador e do circuito auxiliar proposto, bem como o projeto dos sistemas de controle dos mesmos. Resultados de simulação e experimentais comprovam os procedimentos desenvolvidos ao longo do trabalho, bem como validam a funcionalidade do circuito proposto com relação a sua finalidade.

Les Piles à Combustible Microbiennes (PCMs) mettent en œuvre le métabolisme de micro-organismes et utilisent de la matière organique pour générer de l’énergie électrique. Les applications potentielles incluent le traitement de l’eau autonome en énergie, les bio-batteries, et le grappillage d’énergie ambiante. Les PCMs sont des équipements basse-tension et basse-puissance dont le comportement est influencé par la vitesse à laquelle l’énergie électrique est récupérée. Dans cette thèse, on étudie des méthodes pour récupérer l’énergie électrique de façon efficace. La tension à laquelle l’énergie est récupérée des PCMs influence leur fonctionnement et leurs performances électriques. La puissance délivrée est maximum pour une tension spécifique (environ 1/3 de la tension en circuit-ouvert). Les PCMs peuvent être testées à ce point en utilisant une charge contrôlée automatiquement qui inclut un algorithme de recherche de puissance maximale. Un tel outil a été utilisé pour évaluer la puissance maximum, la vitesse de consommation du combustible, le rendement Coulombic et le rendement de conversion de 10 PCMs à chambre unique de 1.3 L construites de façon similaire. Bien que d’autres choix structurels et opératoires peuvent permettre d’améliorer ces performances, ces résultats ont étudié pour la première fois les performances des PCMs en condition de production d’énergie de point de puissance maximal et testé les PCMs avec des conditions de récupération d’énergie réalistes. Récupérer un maximum d’énergie des PCMs est la ligne directrice de ce rapport. C’est rendu possible par des circuits dédiés de gestion de l’énergie qui embarquent un contrôle contre-réactif pour réguler la tension des PCMs à une valeur de référence qui est égale à une fraction de leur tension en circuit ouvert. Deux scénarios typiques sont développés dans la suite. Une application critique des PCMs concerne le grappillage autonome de petites énergies, pour alimenter des équipements électroniques basse-puissance (e.g. capteurs sans fil). Dans ce cas, les contraintes basse-puissance et basse-tension imposées par les PCMs nécessitent des fonctionnalités de démarrage autonomes. L’oscillateur d’Armstrong, composé d’inductances couplées à fort rapport d’enroulement et d’un interrupteur normalement-fermé permet d’élever des tensions de façon autonome à partir de sources basse-tension continue comme les PCMs. Ce circuit a été associé à des convertisseurs d’électronique de puissance AC/DC et DC/DC pour réaliser respectivement un élévateur-de-tension et une unité de gestion de l’énergie (UGE) auto-démarrante basée sur une architecture flyback. La première est adaptée pour les puissances inférieures à 1mW, alors que la seconde peut être dimensionnée pour des niveaux de puissance de quelques mW et permet de mettre en œuvre une commande qui recherche le point de puissance maximale du générateur. Une seconde application d’intérêt concerne le cas où de l’énergie est récupérée depuis plusieurs PCMs. L’association série peut être utilisée pour élever la tension de sortie mais elle peut avoir des conséquences négatives en terme de performances à cause des non-uniformités entre cellules. Cet aspect peut être résolu avec des circuits d’équilibrage de tension. Trois de ces circuits ont été analysés et évalués. Le circuit “complete disconnection” déconnecte une cellule défectueuse de l’association pour s’assurer qu’elle ne diminue pas le rendement global. Le circuit “switched-capacitor” transfère de l’énergie depuis les MFCs fortes vers les faibles pour équilibrer les tensions de toutes les cellules de l’association. Le circuit “switched-MFCs” connecte les PCMs en parallèle et en série de façon alternée. Chacune des trois méthodes peut être mise en œuvre à bas prix et à haut rendement, la plus efficace étant la “switchedcapacitor”qui permet de récupérer plus de 85% de la puissance maximum idéale d’une association très largement non uniforme. / Microbial fuel cells (MFCs) harness the metabolism of micro-organisms and utilize organic matter to generate electrical energy. They are interesting because they accept a wide range of organic matter as a fuel. Potential applications include autonomous wastewater treatment, bio-batteries, and ambient energy scavenging. MFCs are low-voltage, low-power devices that are influenced by the rate at which electrical energy is harvested at their output. In this thesis, we study methods to harvest electrical energy efficiently. The voltage at which energy is harvested from MFCs influences their operation and electrical performance. The output power is maximum for a certain voltage value (approx. 1/3rd the open-circuit voltage). This noteworthy operating point is favorable in some applications where MFCs are used as a power supply. MFCs can be tested at this point using an automatic load adjuster which includes a maximum power point tracking algorithm. Such a tool was used to evaluate the maximum power, the fuel consumption rate, the Coulombic efficiency and the energy conversion efficiency of ten similarly built 1.3 L single-chamber MFCs. Although structural and operating condition choices will lead to improved performance, these results investigate for the first time the performance of MFCs in continuous maximum power point condition and characterize MFCs in realistic energy harvesting conditions. Harvesting energy at maximum power point is the main thread of the manuscript. This is made possible with dedicated energy processing circuits embedding control feedback to regulate the MFC voltage to a fraction of its open-circuit voltage. Two typical scenarios are developed as outlined below. One critical application concerns autonomous low-power energy scavenging, to supply remote low-power electronic devices (e.g. wireless sensors). In this case, the low-power and low-voltage constraints imposed by MFCs require dedicated self start-up features. The Armstrong oscillator, composed of high turn-ratio coupled inductors and of a normally-on switch, permits to autonomously step-up voltages from a low DC source like MFCs. Although the circuit requires few components, its operation is not trivial because it partly relies on the parasitic elements of the inductors and the switch. Proper sizing of the inductors enables an optimized operation. This circuit can be associated with power electronic AC/DCand DC/DC converters to realize a voltage-lifter and a fly back-based self-starting Power Management Unit (PMU) respectively. The former is suitable for powering levels below 1mW, while the latter can be scaled for power levels of a few units of mW and facilitates implementation of maximum power point control. A second application of interest concerns the case where energy is harvested from several MFCs.Serial association can be used to step-up voltage but may lead to detrimental consequences in terms of performances because of hydraulic couplings between MFCs sharing the same electrolyte (e.g. if the MFCs are running in continuous flow) or because of electrical non-uniformities between cells. Whereas the former issue can be addressed with galvanically insulated PMUs, the latter can be solved with voltagebalancing circuits. Three of these latter circuits were analyzed and evaluated. The “complete disconnection” circuit isolates a faulty cell from the configuration to ensure it does not impede the overall efficiency. The “switched-capacitor” circuit transfers energy from the strong to the weak MFCs to equilibrate the voltages of the individual cells in the stack. The “switched-MFC” circuit alternatively connects MFCs in parallel and in series. Each of the three methods can be implemented at low-cost and at high efficiency, the most efficient one being the “switched-capacitor”, that permits to harvest more that 85% of the ideal maximum energy of a strongly-non-uniform MFC association.

No description available.

With the increasing demands on electronic loads (e.g. desktop, laptop, monitor, LED lighting and server) in modern technology-driven lives, performance of switched-mode power supply (SMPS) for electronics have been growing to prominence. As front-end converters in typical SMPS structure, ac-dc power-factor correction (PFC) circuits play a key role in regulations of input power factor, harmonics and dc output voltage, which has a decisive effect on entire power-supply performances. Universal ac-line and low-power system (90–264 Vrms, up to 300–400 W) is one of the most common power-supply specifications and boost-derived PFC topologies have been widely used for the purpose. In order to concurrently achieve high efficiency and low-cost system in the PFC stage, zero-current switching (ZCS) control schemes are highly employed in control principles. Representative schemes are discontinuous conduction mode (DCM) and critical conduction mode (CRM). Both modes can realize ZCS turn-on without diode reverse recovery so that low switching losses and low-cost diode utilizations are obtainable. Among various boost-family PFC topologies, three-level boost (TLB) converter has generated considerable research interest in high-voltage high-power applications. It is mainly due to the fact that the topology can have halved component voltage stresses, improved waveform qualities and electromagnetic interference (EMI) from phase interleaved continuous conduction mode (CCM) operations, compared to other two-level boost PFC converters. On the other hand, in the field of universal-line low-power applications, TLB PFC has been thoroughly out of focus since doubled component counts and increased control complexity than two-level topologies are practical burden for the low-cost systems. However, recent researches on TLB PFC with ZCS control schemes have found that cost-competitiveness of the topology is actually comparable to two-level boost PFC converters because the halved component voltage stresses enable usage of low voltage-rating components of which unit prices are cheaper than higher-rating ones. Based on the justification, researches on ZCS control schemes for TLB PFC have been conducted to get enhanced waveform qualities and performance factors. Following the research stream, a three-level current modulation scheme that can be adopted in both DCM and CRM is proposed in Chapter 2 of this dissertation. Main concept of the proposed current modulation is additional degree-of-freedom in current-slope shaping by differentiating on-times of two active switches, which cannot be found from any other single-phase boost-derived PFC topologies. Using the multilevel feature, proposed operations in one switching period consist of three steps: common-switch on-time, single-switch on-time and common-switch off-time. The single-switch on-time step is key design factor of the proposed modulation that can be utilized either in fixed or adjustable form depending on control purpose. Based on the basic modulation concept, three-level CRM control scheme, adjustable three-level DCM control scheme, and spread-spectrum frequency modulation (SSFM) with adjustable three-level DCM scheme are proposed in Chapter 3–5, respectively. In each chapter, implemented control scheme aims to improve different performance factors. In Chapter 3, the proposed three-level CRM scheme uses increased single-switch on-time period to reduce peak inductor current and magnitude of variable switching frequency. It is generally accepted fact that CRM operations suffer from high switching losses and poor efficiency at light load due to considerable increment of switching frequency. Thus, efficiency improvement effect by the proposed CRM scheme becomes remarkable as load condition goes lighter. In experimental verifications, maximum improvement is measured by 1.2% at light load (20%) and overall efficiency is increased by at least 0.4% all over the load range. In Chapter 4, three-level DCM control scheme adopts adjustable single-switch on-time period in fixed switching-frequency framework. The purpose of adjustable control scheme is to widen the length of non-zero inductor current period as much as possible so that discontinued current period and high peak current of DCM operations can be minimized. Experiment results show that, compared to conventional two-level DCM control, full-load peak inductor currents are reduced by 20.2% and 17.1% at 110 and 220 Vrms input voltage conditions, respectively. Moreover, due to turn-off switching energy decrements by the turn-off current reductions, efficiency is also improved by at least 0.4% regardless of input voltage and load conditions. In Chapter 5, a downward SSFM technique is developed first for DCM operations of boosting PFC converters including two-level topologies. This chapter aims to achieve significant reduction of high differential-mode (DM) EMI amplitudes from DCM operations, which is major drawback of DCM control. By using the simple linearized frequency modulation, peak DM EMI noise at full load condition is reduced by 12.7 dBμV than conventional fixed-frequency DCM control. On top of the proposed SSFM, the adjustable three-level DCM control scheme in Chapter 4 is adopted to get further reductions of EMI noises. Experimental results prove that the collaborations of SSFM and adjustable DCM scheme reduce the EMI amplitudes further by 2.5 dBμV than the result of SSFM itself. The reduced EMI amplitudes are helpful to design input EMI filter with higher cut-off frequency and smaller size. Different from two-level boosting PFC converters, TLB PFC topology has two output capacitors in series and inherently suffers from voltage unbalancing issue, which can be noted as topological trade-off. In Chapter 6, two simple but effective voltage balancing schemes are introduced. The balancing schemes can be easily built into the proposed ZCS control schemes in Chapter 3–5 and experimental results validate the effectiveness of the proposed balancing principles. For all the proposed control schemes in this dissertation, detailed operation principles, derivation process of key equations, comparative analyses, implementation method with digital controller and experimental verifications with TLB PFC prototype are provided. / Doctor of Philosophy / Electronic-based devices and loads have been essential parts of modern society founded on rapid advancements of information technologies. Along with the progress, power supplying and charging of electronic products become routinized in daily lives, but still remain critical requisites for reliable operations. In many power-electronics-based supplying systems, ac-dc power-factor correction (PFC) circuits are generally located at front-end to feed back-end loads from universal ac-line sources. Since PFC stages have a key role in regulating ac-side current quality and dc-side voltage control, the importance of PFC performances cannot be emphasized enough from entire system point of view. Thus, advanced control schemes for PFC converters have been developed in quantity to achieve efficient operations and competent power qualities such as high power factor, low harmonic distortions and low electromagnetic interferences (EMI) noises. In this dissertation, a sort of PFC topologies named three-level boost (TLB) converter is chosen for target topology. Based on inherent three-level waveform capability of the topology, multiple zero-current switching (ZCS) control schemes are proposed. Compared to many conventional two-level PFC topologies, TLB PFC can provide additional degree-of-freedom to current modulation. The increased control flexibility can realize improvements of various waveform qualities including peak current stress, switching frequency range, harmonics and EMI amplitude. From the experimental results in this dissertation, improvements of waveform qualities in TLB PFC with the proposed schemes are verified with comparison to two-level current control schemes; in terms of efficiency, the results show that TLB PFC with the proposed schemes can have similar converter efficiency with conventional two-level boost converter in spite of increased component counts in the topology. Further, the proposed three-level control schemes can be utilized in adjustable forms to accomplish different control objectives depending on system characteristics and applications. In each chapter of this dissertation, a novel control scheme is proposed and explained with details of operation principle, key equations and digital implementation method. All the effectiveness of proposals and analyses are validated by a proper set of experimental results with a TLB PFC prototype.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed. / Master of Science / According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.