Indiana University-Purdue University Indianapolis (IUPUI) / Data network's speed and availability are increasing at a record rate. More and more devices are now able to connect to the Internet and stream data. Processing this ever-growing amount of data in real time continues to be a challenge. Multiple studies have been conducted to address the growing demands for real-time processing and analysis of continuous data streams. Developed in a previous work, Symbiote Coprocessor Unit (SCU) is a hardware accelerator capable of providing up to 150X speedup over traditional data stream processors in the field of data stream management systems. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvements. In this study, we present a new SCU architecture that is based on a Xilinx MicroBlaze configurable microcontroller. The proposed architecture reduces complexity, allows future implementations of new algorithms in a relatively short amount of time while maintaining the SCU's high performance. It also has an industry standard PCIe interface. Finally, it uses a standard AMBA AXI4 bus interconnect, which enables easier integration of new hardware components. The new architecture is implemented using a Xilinx VC709 development board. Our experimental results have shown a minimal loss of performance as compared to the original SCU while providing a flexible and simple design.

<p>With today’s FPGA’s it’s possible to implement complete systems in a single FPGA. With help of Soft Processor Cores like the MicroBlaze processor several microcontrollers can be implemented in the same FPGA.</p><p>The third generation telecommunications system, cdma2000, has several channels, which has specific assignments. The Sync channel purpose is to attain initial time synchronization.</p><p>The purpose with this thesis has been to implement the Sync channel in a FPGA with use of a MicroBlaze processor. An evaluation of the concept of using a Soft Processor Core instead of ordinary DSP’s and microcontrollers would then be conducted.</p><p>This thesis has resulted in a system with a MicroBlaze processor that has the Sync channel as a peripheral. It’s possible to write information via HyperTerminal to the MicroBlaze processor which then uses this data as input to the Sync channel. The Sync channel then modulates the data according to the cdma2000 specifications and then outputs it onto an external pin at the FPGA.</p><p>The evaluation of this concept hasn’t resulted in a general recommendation whether to use ASIC or FPGA’s in a system. The concept of using Soft Processor Cores certainly has its benefits and is something that could be thought of in the future when designing a system.</p>

Actiwave AB delivers audio solutions for active speakers. One of the features is that audio can be streamed to the speakers over a local network connection. The module that provides this functionality is expensive. This thesis investigates if this can instead be achieved by taking advantage of the Spartan-6 FPGA on their platform, using part of it as a MicroBlaze soft processor on which a rendering device can be implemented. The thesis discusses design decisions such as selection and integration of operating system, UPnP framework and media decoder. A fully functional prototype application for a desktop computer was implemented, with the intention of porting it to the FPGA platform. There turned out to be too many compability issues though, so instead, a simpler renderer was implemented on the FPGA. Mp3 music files were successfully streamed to and decoded on the soft processor, but without fulfilling real-time constraints. The conclusion is that it is reasonable to implement a UPnP Media Renderer on the FPGA. Decoding in real-time can be an issue due to insufficient performance of the soft processor, but several possible solutions exist.

With today’s FPGA’s it’s possible to implement complete systems in a single FPGA. With help of Soft Processor Cores like the MicroBlaze processor several microcontrollers can be implemented in the same FPGA. The third generation telecommunications system, cdma2000, has several channels, which has specific assignments. The Sync channel purpose is to attain initial time synchronization. The purpose with this thesis has been to implement the Sync channel in a FPGA with use of a MicroBlaze processor. An evaluation of the concept of using a Soft Processor Core instead of ordinary DSP’s and microcontrollers would then be conducted. This thesis has resulted in a system with a MicroBlaze processor that has the Sync channel as a peripheral. It’s possible to write information via HyperTerminal to the MicroBlaze processor which then uses this data as input to the Sync channel. The Sync channel then modulates the data according to the cdma2000 specifications and then outputs it onto an external pin at the FPGA. The evaluation of this concept hasn’t resulted in a general recommendation whether to use ASIC or FPGA’s in a system. The concept of using Soft Processor Cores certainly has its benefits and is something that could be thought of in the future when designing a system.

One particular application domain of interest for sensor networks is in the real-time processing of audio information for ecological research questions such as species identification. Real-time audio processing generally involves sophisticated signal processing algorithms and requires substantial computational power. As FPGAs increase in capacity and speed but decrease in cost and power consumption, they are now able to provide low-cost, high performance, energy efficient, flexible, and convenient implementations for a wide range of digital systems. This thesis uses the computational power and single-chip solution capabilities of FPGAs to implement a typical audio processing application for sensor networks onto an FPGA using software / hardware co-design approach, and then evaluate the usefulness of this approach. Some background on sensor networks, audio recognition, FPGAs, MicroBlaze and hardware / software co-design is firstly introduced. A few widely adopted feature extraction and pattern matching algorithms are also presented and compared. Several digital signal processing applications based on FPGAs are then reviewed and analyzed. Software / hardware co-design method is then employed to implement an example system. A bird call recognition system based on linear predictive cepstral coefficients and dynamic time warping algorithm is developed and verified on a PC. Then, a software-only solution for this bird call recognition system is implemented on an FPGA with embedded MicroBlaze processor in a Xilinx development board. By means of code profiling, the performance bottlenecks of the software-only solution are identified. Taking the profiling results and the complexity of the recognition algorithm into account, the dynamic time warping algorithm was mapped into custom FPGA hardware. Fast Simplex Links, which are intended specially for high-speed uni-directional transfers to and from the processor, were used to attach the custom hardware to MicroBlaze and pre-defined driver functions supplied by EDK enabled the communications between software and the custom hardware. The software-hardware implementation was then built after substituting custom hardware for software counterparts. The influence of memory assignments for performance is also investigated. External memory access is identified as a major bottleneck. By moving all code from external DRAM into internal BRAM, the system performance is increased by a factor of about 10. From the analysis and comparison of execution time, logic area, and energy consumption of various implementations, it is shown that the software-hardware implementation can speed up a software-only FPGA implementation up to 528 times, and achieves of the order of 20 times “time-area efficiency” and 40 times energy efficiency. Compared with the PC-based C implementation running with a 40 times faster clock rate, the improved software-hardware system runs only about 7 times slower and its performance can meet the real-time requirement to complete a recognition in under one second. In addition, the software / hardware co-design also significantly reduces the energy consumption associated with individual computations.

Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall, en Virtex4 FX12 från Xilinx. System med de olika kärnorna har tagits fram, där antalet klockcykler för att genomföra olika beräkningar har mäts. Bland annat har algoritmen Fast Fourier Transform och dess invers beräknats för en vektor. De kärnor som har provats är den mjuka MicroBlaze framtagen av Xilinx samt den hårda PowerPC 405. Prestandan för systemet med mjuk kärna var 65 % av det med hård kärna Förutom prestandamätningarna har en vidare teoretisk jämförelse mellan kärnorna genomförts. Utifrån den har slutsatsen dragits att när man behöver små volymer av FPGA-kretsar eller flera olika beräkningar skall göras är FPGAer med hård kärna att föredra. Om det är större volymer eller bara ett fåtal typer av beräkningar som skall utföras är en mjuk kärna mest fördelaktig, främst av ekonomiska skäl. Likaså om krav finns på att processorarkitekturen är anpassad efter specifika önskemål. / The purpose of the master thesis has been implementation of a performance comparison between hard and soft CPU cores integrated in FPGA, in this case, a Virtex4 FX12 from Xilinx. Test designs for the various kernels have been developed, where the amount of clock cycles to carry out a set of calculations have been measured. In particular, the algorithm Fast Fourier Transform and its inverse have been studied. The cores that have been tested are the soft MicroBlaze developed by Xilinx, and the hard PowerPC 405. The results state that the performance of the soft kernel was 65% of the hard one. In addition to performance tests, a further theoretical comparison of the two kernels has been made. On the basis of the above it has been concluded that when small quantities of FPGA-circuits are needed or several different calculations have to be done, a hard core is preferable. If there are larger volumes needed or just a few types of calculations to be made, a soft core is advantageous, primarily for economic reasons, as is the case if there is requirement of a processor core tailored for specific needs.

<p> </p><p>Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall, en Virtex4 FX12 från Xilinx.</p><p>System med de olika kärnorna har tagits fram, där antalet klockcykler för att genomföra olika beräkningar har mäts. Bland annat har algoritmen Fast Fourier Transform och dess invers beräknats för en vektor.</p><p>De kärnor som har provats är den mjuka MicroBlaze framtagen av Xilinx samt den hårda PowerPC 405. Prestandan för systemet med mjuk kärna var 65 % av det med hård kärna</p><p>Förutom prestandamätningarna har en vidare teoretisk jämförelse mellan kärnorna genomförts. Utifrån den har slutsatsen dragits att när man behöver små volymer av FPGA-kretsar eller flera olika beräkningar skall göras är FPGAer med hård kärna att föredra. Om det är större volymer eller bara ett fåtal typer av beräkningar som skall utföras är en mjuk kärna mest fördelaktig, främst av ekonomiska skäl. Likaså om krav finns på att processorarkitekturen är anpassad efter specifika önskemål.</p> / <p>The purpose of the master thesis has been implementation of a performance comparison between hard and soft CPU cores integrated in FPGA, in this case, a <em>Virtex4 FX12</em> from Xilinx.</p><p>Test designs for the various kernels have been developed, where the amount of clock cycles to carry out a set of calculations have been measured. In particular, the algorithm Fast Fourier Transform and its inverse have been studied.</p><p>The cores that have been tested are the soft MicroBlaze developed by Xilinx, and the hard PowerPC 405. The results state that the performance of the soft kernel was 65% of the hard one.</p><p>In addition to performance tests, a further theoretical comparison of the two kernels has been made. On the basis of the above it has been concluded that when small quantities of FPGA-circuits are needed or several different calculations have to be done, a hard core is preferable. If there are larger volumes needed or just a few types of calculations to be made, a soft core is advantageous, primarily for economic reasons, as is the case if there is requirement of a processor core tailored for specific needs.</p>

Navigation algorithms integrating measurements from multi-sensor systems overcome the problems that arise from using GPS navigation systems in standalone mode. Algorithms which integrate the data from 2D low-cost reduced inertial sensor system, consisting of a gyroscope and an odometer, along with a GPS via a Kalman filter has proved to be worthy in providing a consistent and more reliable navigation solution compared to the standalone GPS. It has been also shown to be beneficial, especially in GPS-denied environments such as urban canyons and tunnels. The main objective of this research is to narrow the idea-to-implementation gap that follows the algorithm development by realizing a low-cost real-time embedded navigation system that is capable of computing the data-fused positioning solution instantly. The role of the developed system is to synchronize the measurements from the three sensors, GPS, gyroscope and odometer, relative to the pulse per second signal generated from the GPS, after which the navigation algorithm is applied to the synchronized measurements to compute the navigation solution in real-time. Xilinx’s MicroBlaze soft-core processor on a Virtex-4 FPGA is utilized and customized for developing the real-time navigation system. The soft-core processor offers the flexibility to choose or implement a set of features and peripherals that are tailored to the specific application to be developed. An embedded system design model is chosen to act as a framework for the work flow to be carried through the system life cycle starting from the system specification phase and ending with the system release. The developed navigation system is tested first on a mobile robot to reveal system bugs and integration problems, and then on a land vehicle testing platform for further testing. The real-time solution from the implemented system when compared to the solution of a high-end navigation system, proved to be successful in providing a comparable consistent real-time navigation solution. Employing a soft-core processor in the kernel of the navigation system, provided the flexibility for communicating with the various sensors and the computation capability required by the Kalman filter integration algorithm. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-10-11 16:08:38.811

This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.

The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in the microarchitecture of the processor. It also introduces design of processors using CodAL language developed by Codasip company. In the practical part of the thesis the model of MicroBlaze core developed by Xilinx company was described in the CodAL language. Designed model was tested and implemented into the FPGA device as practical example.